基于交点队列型Crossbar的多层AXI总线设计
发布时间：2018-12-10 12:07
【摘要】：AXI总线内部传统的核间通信结构对处理器核之间的通信存在多方面的限制,已难以满足多核SoC(System on Chip)日益发展的性能需求。提出以交点队列(Crosspiont-Queued,CQ)型Crossbar代替传统的核间通信结构,设计一种多层AXI总线。通过Simulink工具对交点队列型核间通信结构进行建模与仿真,确定其交点缓存的最佳深度。并结合VCS仿真工具对所设计的RTL代码进行了全方面的仿真,结果表明,所设计的通信架构能够完整地实现读写功能。
[Abstract]:The traditional inter-core communication architecture in AXI bus has many limitations on the communication between processor cores, which makes it difficult to meet the growing performance requirements of multi-core SoC (System on Chip). In this paper, a multi-layer AXI bus is designed by replacing the traditional inter-core communication structure with the intersection queue (Crosspiont-Queued,CQ) type Crossbar. The intercore communication structure of intersection queue type is modeled and simulated by Simulink tool, and the optimum depth of intersecting buffer is determined. Combined with the VCS simulation tool, the designed RTL code is simulated in all aspects. The results show that the designed communication architecture can complete the function of reading and writing.
【作者单位】： 苏州大学电子信息学院;中国兵器工业集团北方电子研究院有限公司微电子部;
【分类号】：TP336
本文编号：2370541
[Abstract]:The traditional inter-core communication architecture in AXI bus has many limitations on the communication between processor cores, which makes it difficult to meet the growing performance requirements of multi-core SoC (System on Chip). In this paper, a multi-layer AXI bus is designed by replacing the traditional inter-core communication structure with the intersection queue (Crosspiont-Queued,CQ) type Crossbar. The intercore communication structure of intersection queue type is modeled and simulated by Simulink tool, and the optimum depth of intersecting buffer is determined. Combined with the VCS simulation tool, the designed RTL code is simulated in all aspects. The results show that the designed communication architecture can complete the function of reading and writing.
【作者单位】： 苏州大学电子信息学院;中国兵器工业集团北方电子研究院有限公司微电子部;
【分类号】：TP336
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