基于Flash阵列的高速存储及可靠性设计

发布时间：2018-12-21 13:53

【摘要】：在图像数据采集中,存储体系需要满足对图像数据持续高速存储的要求。针对某图像信息处理器的性能测试需求,开发了图像数据的高速并行化存储体系。为实现图像数据的大容量、高速、高可靠、低功耗的存储需求,本文致力于研究一种图像数据高速存储方法,并对高速存储涉及的高可靠低功耗进行了深入研究。首先,为了实现200 MB/s的持续存储速度,借鉴流水线和并行扩展的思路,设计了一种结构为5×8的Flash存储阵列。以状态机实现通道内和通道间的流水线设计,通过双流水线形式的并行工作模式,充分发挥每一片NAND Flash的存储性能以实现图像数据的持续高速存储。其次,在可靠性方面,针对Flash阵列的无效块管理问题,提出了两种无效块管理方案,并分析了两种无效块管理方案的优缺点,选择了基于组合块理念的无效块管理方案;同时,为了解决突发无效块对高速存储的影响,设计了滞后重写机制。另外,针对Flash芯片单比特翻转造成的数据误码,提出了双缓存交替的汉明码纠错方案,该方案在不影响数据读取速度的情况下,有效避免了Flash的单比特误码的产生。最后,为了降低FPGA功耗,减少芯片发热,提出了一种程序低功耗优化方法,采用这种设计方法可以大幅减小内部的逻辑资源、布线资源的使用,从而达到降低动态功耗,提高FPGA程序运行可靠性的目的。通过对各项技术指标以及系统总体的性能进行测试,并分析得到的测试数据,设计的Flash阵列可以达到200MB/s的数据存储速率。通过大量试验证明,存储体系的存储速率以及容量均满足设计指标,工作稳定可靠。
[Abstract]:In image data acquisition, the storage system needs to meet the requirements of image data storage. A high speed parallel storage system for image data is developed to meet the performance test requirements of an image information processor. In order to realize the storage requirements of large capacity, high speed, high reliability and low power consumption of image data, this paper focuses on a high speed storage method of image data, and deeply studies the high reliability and low power consumption involved in high speed storage. Firstly, in order to realize the continuous storage speed of 200 MB/s, a 5 脳 8 Flash memory array is designed based on the idea of pipeline and parallel expansion. The state machine is used to design pipeline in and between channels, and the storage performance of each piece of NAND Flash is brought into full play through the parallel working mode in the form of dual pipeline to realize the continuous high speed storage of image data. Secondly, in the aspect of reliability, aiming at the invalid block management of Flash array, two invalid block management schemes are proposed, and the advantages and disadvantages of two invalid block management schemes are analyzed, and the invalid block management scheme based on composite block concept is selected. At the same time, in order to solve the impact of burst invalid block on high speed storage, a delay rewriting mechanism is designed. In addition, aiming at the data error caused by single bit flipping in Flash chip, a double buffer alternating hamming code correction scheme is proposed, which can effectively avoid the generation of single bit error code of Flash without affecting the data reading speed. Finally, in order to reduce FPGA power consumption and chip heating, a program low-power optimization method is proposed, which can greatly reduce the use of internal logic resources and wiring resources, thereby reducing the dynamic power consumption. The purpose of improving the reliability of FPGA program. By testing the technical specifications and the overall performance of the system, and analyzing the test data, the designed Flash array can achieve the data storage rate of 200MB/s. Through a lot of experiments, it is proved that the storage rate and capacity of the storage system meet the design index and work stably and reliably.
【学位授予单位】：中北大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP333;TP391.41

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