宽范围全数字逐次逼近寄存器延时锁定环的设计

发布时间：2018-12-27 15:24

【摘要】：随着半导体工艺的快速发展,芯片中集成的CMOS晶体管数量已经多达23亿个,向着系统芯片发展。系统芯片对工作频率的要求也越来越高,在工作频率已经达到吉赫兹的时代,时钟偏差无疑成为其前进路上的绊脚石。延时锁定环被广泛地用在各类集成电路中,以期望最大限度地减少时钟偏差。目前全数字延时锁定环主要分为三类,分别为移位寄存器延时锁定环、计数器延时锁定环和逐次逼近寄存器延时锁定环。逐次逼近寄存器延时锁定环因其锁定速度快被备受设计人员的青睐。传统逐次逼近寄存器延时锁定环虽然锁定速度快,但是由于其采用了差分式延时单元,即使数据从快速传输路径传输,也存在着一个固定的延时,并且数据从慢速传输路径和快速传输路径所用的时间差不是很大,使得传统逐次逼近寄存器延时锁定环存在着锁定范围窄的缺点；同时,差分式延时单元采用了定制的电容元件,使得其设计不方便。本论文研究的重点是在传统逐次逼近寄存器延时锁定环的基础上,采用标准逻辑门搭建延时单元,相比较于差分延时单元,设计方便,并且延时变化范围大,使改进后的逐次逼近寄存器延时锁定环具有很宽的锁定范围。本论文合理地选用电子设计自动化工具搭建实现平台,采用中芯国际集成电路制造公司的CMOS0.18μm1P6M工艺在该平台上实现了改进后的宽范围全数字逐次逼近寄存器延时锁定环。在典型情况下,利用仿真器HSIM对改进后的宽范围全数字逐次逼近寄存器延时锁定环的晶体管级电路进行了仿真,结果表明改进后的宽范围全数字逐次逼近寄存器延时锁定环的锁定范围在200MHz到670MHz之间,达到了改进目标。
[Abstract]:With the rapid development of semiconductor technology, the number of integrated CMOS transistors in the chip has reached 2.3 billion, developing towards the system chip. The working frequency of the system chip is more and more high. In the age of GHz, the clock deviation is undoubtedly the stumbling block on the way forward. Delay locking rings are widely used in various integrated circuits in order to minimize clock bias. At present all digital delay locking rings are divided into three categories: shift register delay locking ring counter delay lock ring and successive approximation register delay lock ring. Successive approximation register delay locking loop is favored by designers for its fast locking speed. Although the locking speed of the traditional successive approximation register delay locking loop is fast, but because of its differential delay unit, even if the data is transmitted from the fast transmission path, there is a fixed delay. And the time difference between slow transmission path and fast transmission path is not very large, which makes the traditional successive approximation register delay locking loop have the disadvantage of narrow locking range. At the same time, the differential delay unit uses the customized capacitor element, which makes its design inconvenient. On the basis of the traditional successive approximation register delay locking loop, this paper uses the standard logic gate to build the delay unit. Compared with the differential delay unit, the design is convenient and the delay range is large. The improved successive approximation register delay locking loop has a wide locking range. In this paper, the electronic design automation tools are reasonably selected to build the implementation platform, and the improved full digital successive approximation register delay locking ring is realized on the platform using the CMOS0.18 渭 m1P6M process of SMIC. In the typical case, the transistor-level circuit of the improved full-digital successive approximation register delay-locking ring is simulated by using the simulator HSIM. The results show that the locking range of the improved all-digital successive approximation register delay-locking ring is between 200MHz and 670MHz, and the improved target is achieved.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333;TN402

【相似文献】