基于SRAM型FPGA的抗单粒子效应容错技术的研究

发布时间：2019-01-12 10:36

【摘要】：SRAM型FPGA具有开发成本低，高密度等特性，使得其逐步应用到航空航天领域，但由于SRAM型FPGA是易失性存储，很容易受到单粒子效应的影响。国外对FPGA的单粒子效应检测和加固方面进行了大量工作，生成了多种FPGA的测试报告。目前，国内主要进行FPGA的单粒子检测，对FPGA的容错加固的研究还很少。因此，本文通过研究FPGA的基本结构和工作原理，分析研究SRAM型FPGA的单粒子效应，特别是SEU对FPGA的影响。针对现有的SEU缓解技术展开了一系列的研究，主要工作与创新如下： 1.由于传统TMR设计的容错系统受制于多数表决器（Voter），因此，深入研究了Xilinx提出的XTMR方法， XTMR方法可以使在三模冗余中的任何一条路径发生SEU时都能输出正确的结果。 2.从TMR和EDAC两个方面对BRAM加固进行研究，实现了用汉明码对任意数据位宽度的存储器加固，为了纠正多比特数据翻转，提出了用RM(2,5)码加固BRAM存储器。另一方面，考虑到EDAC模块本身不具有抗辐射的能力，提出了对EDAC模块进行三模冗余加固设计。 3.由于Virtex-4器件具有回读和动态重配置功能，本文深入研究其配置过程，配置原理以及容错设计中采用的擦洗、回读技术等。 4.根据现有的容错方法设计一些容错功能电路。实现了移位寄存器和UART的三模冗余设计。分别用综合约束和Hamming-3码实现了状态机的抗SEU。结合EDAC和TMR方法设计了容错异步串行收发器IP核，，并进行故障注入仿真，仿真结果表明达到设计要求。最后，通过分析单粒子效应对FPGA的影响，针对实际工程对系统可靠性和性能等方面的要求给出了电路设计容错加固策略。
[Abstract]:SRAM type FPGA has the characteristics of low development cost and high density, which makes it applied to aerospace field step by step. However, because SRAM type FPGA is volatile storage, it is easy to be affected by single particle effect. A great deal of work has been done in the field of single particle effect detection and reinforcement of FPGA abroad, and a variety of FPGA test reports have been generated. At present, the single particle detection of FPGA is mainly carried out in China, and the research on fault tolerant reinforcement of FPGA is still rare. Therefore, by studying the basic structure and working principle of FPGA, the single particle effect of SRAM type FPGA, especially the influence of SEU on FPGA, is analyzed. A series of research on the existing SEU mitigation technology has been carried out. The main work and innovation are as follows: 1. Because the fault tolerant system designed by traditional TMR is subject to the majority of determinators (Voter), the XTMR method proposed by Xilinx is studied in depth. The XTMR method can output correct results when any path in tri-mode redundancy occurs SEU. 2. The reinforcement of BRAM is studied from two aspects of TMR and EDAC. The hamming code is used to reinforce the memory of any data bit width. In order to correct the multi-bit data flipping, the RM (2P5) code is proposed to reinforce the BRAM memory. On the other hand, considering that the EDAC module itself does not have the ability to resist radiation, a three-mode redundant reinforcement design for the EDAC module is proposed. 3. Because Virtex-4 devices have the functions of backreading and dynamic reconfiguration, the configuration process, configuration principle, scrubbing and rereading techniques used in fault-tolerant design are studied in this paper. 4. Some fault-tolerant function circuits are designed according to the existing fault-tolerant methods. The design of shift register and UART is realized. The anti-SEU. of state machine is realized by synthesizing constraint and Hamming-3 code, respectively. The fault-tolerant asynchronous serial transceiver IP core is designed based on EDAC and TMR method, and the fault injection simulation is carried out. The simulation results show that the design requirements are met. Finally, by analyzing the effect of single particle effect on FPGA, the fault-tolerant reinforcement strategy of circuit design is proposed to meet the requirements of system reliability and performance in practical engineering.
【学位授予单位】：西北师范大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333;TN791

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