金属浮栅存储器的结构优化和性能分析
发布时间：2019-01-18 16:08
【摘要】：Flash存储器由于其高集成度、低功耗、高可靠性和高性价比等优点,在非易失性存储器市场中占据了主要的份额。但随着微电子技术的发展,Flash存储器也面临了一系列的挑战,如更低的功耗,更快的速度,更高的集成度等。对于传统多晶硅浮栅存储器而言,多晶硅浮栅的厚度随着器件特征尺寸的减小而同步减薄,这使得具有高能量的入射电子增多。大量的高能入射电子对阻挡氧化层造成损伤,产生更多的陷阱和缺陷,影响器件的可靠性。为了克服这一问题,以金属替代多晶硅作为浮栅的方案被提出来,因此对金属浮栅存储器性能的研究和改善得到了比较广泛的关注。本论文主要以金属浮栅存储器为研究对象,通过对浮栅结构进行优化,改进存储器编程/擦除性能。金属浮栅存储器的浮栅材料的功函数对器件性能有很大影响,因此本论文首先对浮栅材料的功函数对器件性能的影响做了研究。在此基础上通过调整和优化金属浮栅结构,改变沟道内电场分布和浮栅耦合电势,研究了金属浮栅结构对存储器性能的影响。结果表明,对金属浮栅结构进行优化后,沟道电场分布出现局部峰值,提升了沟道内热电子的动能,从而促进编程过程中电子的注入效率;同时,浮栅中耦合的电势也得到提升,进而增强编程过程中的垂直电场,进一步提高热电子的注入效率。在擦除过程中,由于垂直电场的增强,使存储在金属浮栅中的电荷更容易通过F-N隧穿回到衬底。通过对比,优化后的器件在相同的阈值电压改变量(编程和擦除过程中分别为3.5V和-3.5V)情况下所需的编程时间缩短了77%,擦除时间缩短了52%,器件的编程/擦除性能得到了提升。SOI技术对器件性能有很大的影响,因此本论文研究了SOI衬底上的金属浮栅存储器的性能,并提出了改进方案。模拟结果表明,SOI顶层硅厚度为5nm时存储器的编程和擦除性能达到最优。在此基础上,本论文对在SOI衬底上的金属浮栅存储器的浮栅结构也进行了优化。优化后存储器的存储窗口提升了32%,并且在相同的阈值电压改变量(编程和擦除过程中分别为3.5V和-3.5V)情况下所需的编程时间缩短了73%,擦除时间缩短了64%。在此基础上本论文研究了高k材料作为器件控制栅介质层时对器件性能的影响。仿真结果表明,高k材料作为控制栅介质层能进一步提升器件的编程/擦除性能。最后,设计了一种制造优化的SOI金属浮栅存储器的工艺流程,该工艺与标准硅CMOS技术相兼容。借助Silvaco TCAD工艺模拟工具,论文中模拟了SOI金属浮栅存储器的工艺流程。通过模拟仿真,证实了本文提出的方案的可行性。
[Abstract]:Because of its advantages of high integration, low power consumption, high reliability and high cost performance, Flash memory occupies a major share in the non-volatile memory market. However, with the development of microelectronics technology, Flash memory also faces a series of challenges, such as lower power consumption, faster speed, higher integration and so on. For the conventional polysilicon floating gate memory, the thickness of the polysilicon floating gate decreases synchronously with the decrease of the characteristic size of the device, which makes the incident electrons with high energy increase. A large number of high energy incident electrons damage the oxide barrier and produce more traps and defects which affect the reliability of the device. In order to overcome this problem, the scheme of metal instead of polysilicon as floating gate has been put forward, so the research and improvement of metal floating gate memory have been paid more attention. In this paper, the metal floating gate memory is studied, and the memory programming / erasing performance is improved by optimizing the floating gate structure. The work function of the floating gate material of metal floating gate memory has great influence on the performance of the device, so the influence of the work function of the floating gate material on the performance of the device is studied in this paper. On this basis, the influence of metal floating gate structure on memory performance is studied by adjusting and optimizing the metal floating gate structure, changing the electric field distribution in the channel and the floating gate coupling potential. The results show that after the optimization of the metal floating gate structure, the local peak value of the channel electric field appears, which enhances the kinetic energy of the hot electron in the channel and thus promotes the efficiency of electron injection in the programming process. At the same time, the coupling potential in the floating gate is also enhanced, which enhances the vertical electric field in the programming process and further improves the injection efficiency of hot electrons. During the erasure process the charge stored in the metal floating gate is easier to return to the substrate through the F-N tunneling due to the enhancement of the vertical electric field. By comparison, the optimized device reduces the programming time and erasure time by 7777V and 52V respectively under the same threshold voltage change (3.5V and -3.5V in programming and erasing process, respectively). The programming / erasure performance of the device has been improved. The SOI technology has great influence on the device performance. Therefore, the performance of metal floating gate memory on SOI substrate is studied in this paper, and an improved scheme is proposed. The simulation results show that the memory programming and erasure performance is optimal when the top silicon thickness of SOI is 5nm. On this basis, the floating gate structure of metal floating gate memory on SOI substrate is also optimized. The memory window of the optimized memory is increased by 32 and the programming time and the erasure time are shortened by 73 and 64 respectively in the case of the same threshold voltage change (3.5V and -3.5V in the programming and erasure process respectively). On this basis, the effect of high k material as gate dielectric layer on device performance is studied. The simulation results show that the high k material as the control gate dielectric layer can further improve the programming / erasure performance of the device. Finally, a process of manufacturing optimized SOI metal floating gate memory is designed, which is compatible with standard silicon CMOS technology. With the aid of Silvaco TCAD process simulation tool, the process of SOI metal floating gate memory is simulated in this paper. The feasibility of the proposed scheme is verified by simulation.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP333
[Abstract]:Because of its advantages of high integration, low power consumption, high reliability and high cost performance, Flash memory occupies a major share in the non-volatile memory market. However, with the development of microelectronics technology, Flash memory also faces a series of challenges, such as lower power consumption, faster speed, higher integration and so on. For the conventional polysilicon floating gate memory, the thickness of the polysilicon floating gate decreases synchronously with the decrease of the characteristic size of the device, which makes the incident electrons with high energy increase. A large number of high energy incident electrons damage the oxide barrier and produce more traps and defects which affect the reliability of the device. In order to overcome this problem, the scheme of metal instead of polysilicon as floating gate has been put forward, so the research and improvement of metal floating gate memory have been paid more attention. In this paper, the metal floating gate memory is studied, and the memory programming / erasing performance is improved by optimizing the floating gate structure. The work function of the floating gate material of metal floating gate memory has great influence on the performance of the device, so the influence of the work function of the floating gate material on the performance of the device is studied in this paper. On this basis, the influence of metal floating gate structure on memory performance is studied by adjusting and optimizing the metal floating gate structure, changing the electric field distribution in the channel and the floating gate coupling potential. The results show that after the optimization of the metal floating gate structure, the local peak value of the channel electric field appears, which enhances the kinetic energy of the hot electron in the channel and thus promotes the efficiency of electron injection in the programming process. At the same time, the coupling potential in the floating gate is also enhanced, which enhances the vertical electric field in the programming process and further improves the injection efficiency of hot electrons. During the erasure process the charge stored in the metal floating gate is easier to return to the substrate through the F-N tunneling due to the enhancement of the vertical electric field. By comparison, the optimized device reduces the programming time and erasure time by 7777V and 52V respectively under the same threshold voltage change (3.5V and -3.5V in programming and erasing process, respectively). The programming / erasure performance of the device has been improved. The SOI technology has great influence on the device performance. Therefore, the performance of metal floating gate memory on SOI substrate is studied in this paper, and an improved scheme is proposed. The simulation results show that the memory programming and erasure performance is optimal when the top silicon thickness of SOI is 5nm. On this basis, the floating gate structure of metal floating gate memory on SOI substrate is also optimized. The memory window of the optimized memory is increased by 32 and the programming time and the erasure time are shortened by 73 and 64 respectively in the case of the same threshold voltage change (3.5V and -3.5V in the programming and erasure process respectively). On this basis, the effect of high k material as gate dielectric layer on device performance is studied. The simulation results show that the high k material as the control gate dielectric layer can further improve the programming / erasure performance of the device. Finally, a process of manufacturing optimized SOI metal floating gate memory is designed, which is compatible with standard silicon CMOS technology. With the aid of Silvaco TCAD process simulation tool, the process of SOI metal floating gate memory is simulated in this paper. The feasibility of the proposed scheme is verified by simulation.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP333
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