SRAM IP实速测试系统设计与测试
发布时间：2019-02-16 08:20
【摘要】：随着集成电路特征尺寸不断减小和电路工作频率的不断提高,存储器故障不再是简单的功能故障,由于电路的微弱延时引起的性能故障也成为了集成电路设计和测试中必须考虑的问题。本文以存储器内建自测试技术作为基础,研究静态随机存储器SRAM实速测试芯片的设计及测试,提出了一种基于改进的算法设计的BIST系统,并利用止(?)BIST扩展设计了实速测试系统,同时分析了存储器实速测试的原理,以所设计的实速测试芯片对SRAM IP进行了测试。 SRAM实速测试的测试对象是SRAM IP的功能测试和性能测试。对于功能测试,本文首先分析了存储器常见的故障类型,研究了几种普遍采用的存储器测试算法,在此基础上提出了一种由改进March C+算法和棋盘法测试结合的测试图形产生机制,改进后的算法可以有效地检测传统March C算法不能检测的耦合失效和临近图形敏感失效。基于改进的算法,以自顶向下的理念设计了内建自测试电路并予以硬件实现和仿真,仿真结果标明所设计的BIST能够在多数据背景下以较快速度遍历。所设计的BIST电路实现了较高的故障检查覆盖率和较快的测试速度,具有良好的复用性。 对于SRAM的性能测试,本文对所设计的BIST进行扩展,加入全数字锁相环和延时链电路。利用ADPLL产生的高频时钟和片外可调选项提供芯片模拟用户使用的多频率测试环境,利用延时电路和片外可调选项量取SRAM的存取时间等性能参数。本文对实速测试芯片量取SRAM性能参数的原理和测试过程做了详尽叙述,并在25℃TT工艺角400MHz至设计预仿真值频率的测试环境下对实速测试芯片进行测试。最后将所测试结果与SRAM设计师的预仿真值进行比较,得出所设计的实速测试芯片功能和性能都达到了设计规范中制定的设计指标。 实速测试芯片已经以55nm SPRVT1P10M low-K工艺流片交付使用,已用于寄存器文件型单端口SRAM IP的测试。封装类型是QFP100。
[Abstract]:With the decreasing of IC feature size and the increasing of circuit working frequency, the memory fault is no longer a simple functional fault. The performance failure caused by the weak delay of the circuit has also become a problem that must be considered in the design and testing of integrated circuits. Based on memory built-in self-test technology, this paper studies the design and test of SRAM real speed test chip for static random access memory, and proposes a BIST system based on improved algorithm design. The real speed testing system is designed by using the BIST extension, and the principle of memory real speed testing is analyzed. The SRAM IP is tested with the designed real speed test chip. The test object of SRAM real-speed test is the function test and performance test of SRAM IP. For function testing, this paper first analyzes the common fault types of memory, and studies several commonly used memory testing algorithms. On this basis, a test graph generation mechanism combining improved March C algorithm and chessboard test is proposed. The improved algorithm can effectively detect coupling failure and near graph sensitive failure that can not be detected by traditional March C algorithm. Based on the improved algorithm, the built-in self-test circuit is designed with the top-down idea, and the hardware implementation and simulation are given. The simulation results show that the designed BIST can traverse in a faster speed under multi-data background. The designed BIST circuit has high fault detection coverage and fast test speed, and has good reusability. For the performance test of SRAM, we extend the designed BIST, add all digital PLL and delay chain circuit. The high frequency clock and off-chip tunable options generated by ADPLL are used to provide a multi-frequency test environment for analog users of the chip. The delay circuit and off-chip tunable options are used to measure the access time of SRAM and other performance parameters. In this paper, the principle and testing process of measuring SRAM performance parameters for real speed test chip are described in detail, and the real speed test chip is tested under the test environment of 25 鈩，
本文编号：2424243
[Abstract]:With the decreasing of IC feature size and the increasing of circuit working frequency, the memory fault is no longer a simple functional fault. The performance failure caused by the weak delay of the circuit has also become a problem that must be considered in the design and testing of integrated circuits. Based on memory built-in self-test technology, this paper studies the design and test of SRAM real speed test chip for static random access memory, and proposes a BIST system based on improved algorithm design. The real speed testing system is designed by using the BIST extension, and the principle of memory real speed testing is analyzed. The SRAM IP is tested with the designed real speed test chip. The test object of SRAM real-speed test is the function test and performance test of SRAM IP. For function testing, this paper first analyzes the common fault types of memory, and studies several commonly used memory testing algorithms. On this basis, a test graph generation mechanism combining improved March C algorithm and chessboard test is proposed. The improved algorithm can effectively detect coupling failure and near graph sensitive failure that can not be detected by traditional March C algorithm. Based on the improved algorithm, the built-in self-test circuit is designed with the top-down idea, and the hardware implementation and simulation are given. The simulation results show that the designed BIST can traverse in a faster speed under multi-data background. The designed BIST circuit has high fault detection coverage and fast test speed, and has good reusability. For the performance test of SRAM, we extend the designed BIST, add all digital PLL and delay chain circuit. The high frequency clock and off-chip tunable options generated by ADPLL are used to provide a multi-frequency test environment for analog users of the chip. The delay circuit and off-chip tunable options are used to measure the access time of SRAM and other performance parameters. In this paper, the principle and testing process of measuring SRAM performance parameters for real speed test chip are described in detail, and the real speed test chip is tested under the test environment of 25 鈩，
本文编号：2424243
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