网络处理器微引擎的设计、验证与实现
发布时间：2019-03-03 14:16
【摘要】：随着互联网的普及，网络带宽不断增大，新型业务不断出现，这些都对网络数据处理设备提出了高性能、可编程的要求，网络处理器正是在这样的背景下产生的。作为网络处理器的数据处理核心，微引擎处理器扮演着重要角色，它的性能很大程度上决定了网络处理器的数据处理能力。 本文重点设计了一款可编程、高性能的微引擎处理器。它使用了可编程的指令存储器，可以适应不断变化的网络协议和新型业务；指令集方面针对常用的网络处理进行了优化，设计了针对网络特殊应用的循环冗余校验、FFS等指令；采用了五级流水线结构，提高了系统性能，使单个微引擎的速度达到了250MHz；设置了特殊的数据存储器，如邻居寄存器和本地存储器，并使用灵活多样的寻址方式，达到了线程间数据隔离和共享的目的；使用了事件信号来同步外设的访问和线程切换；硬件多线程是微引擎的一大特点，采用了基于事件信号的主动式的线程切换，多个线程使用轮询的仲裁策略，通过上下文切换共享一条流水线，可以提高流水线的执行效率。本文还搭建了验证平台，对微引擎的所有指令进行代码仿真，针对关键技术点做了焦点验证。最后在SMIC0.13μm的工艺条件下对RTL代码进行逻辑综合，，结果表明该设计的工作频率可以达到250MHz。
[Abstract]:With the popularization of the Internet, the increasing bandwidth and the emergence of new services, the network data processing equipment is required for high performance and programmability. The network processor is produced under this background. As the data processing core of network processor, micro-engine processor plays an important role, and its performance determines the data processing ability of network processor to a great extent. This paper focuses on the design of a programmable, high-performance micro-engine processor. It uses programmable instruction memory and can adapt to the changing network protocols and new services, the instruction set is optimized for the commonly used network processing, and the cyclic redundancy check, FFS and other instructions are designed for the special application of the network. A five-stage pipeline structure is adopted to improve the performance of the system, and the speed of a single micro-engine is up to 250 MHz. Special data memory, such as neighbor register and local memory, is set up, and flexible and diverse addressing methods are used to achieve the purpose of data isolation and sharing between threads, and event signals are used to synchronize access and thread switching of peripheral devices. Hardware multithreading is one of the main characteristics of micro-engine. Active thread switching based on event signal is adopted. Multiple threads use polling arbitration strategy to share a pipeline through context switching, which can improve the efficiency of pipeline execution. In this paper, a verification platform is built to simulate all the instructions of the micro-engine, and focus verification is made against the key technical points. Finally, the logic synthesis of RTL code is carried out under the condition of SMIC 0.13 渭 m. The results show that the working frequency of the design can reach 250 MHz.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
本文编号：2433774
[Abstract]:With the popularization of the Internet, the increasing bandwidth and the emergence of new services, the network data processing equipment is required for high performance and programmability. The network processor is produced under this background. As the data processing core of network processor, micro-engine processor plays an important role, and its performance determines the data processing ability of network processor to a great extent. This paper focuses on the design of a programmable, high-performance micro-engine processor. It uses programmable instruction memory and can adapt to the changing network protocols and new services, the instruction set is optimized for the commonly used network processing, and the cyclic redundancy check, FFS and other instructions are designed for the special application of the network. A five-stage pipeline structure is adopted to improve the performance of the system, and the speed of a single micro-engine is up to 250 MHz. Special data memory, such as neighbor register and local memory, is set up, and flexible and diverse addressing methods are used to achieve the purpose of data isolation and sharing between threads, and event signals are used to synchronize access and thread switching of peripheral devices. Hardware multithreading is one of the main characteristics of micro-engine. Active thread switching based on event signal is adopted. Multiple threads use polling arbitration strategy to share a pipeline through context switching, which can improve the efficiency of pipeline execution. In this paper, a verification platform is built to simulate all the instructions of the micro-engine, and focus verification is made against the key technical points. Finally, the logic synthesis of RTL code is carried out under the condition of SMIC 0.13 渭 m. The results show that the working frequency of the design can reach 250 MHz.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
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