某电子控制系统自动测试系统开发及SRAM内建测试方法研究

发布时间：2019-03-16 14:15

【摘要】：本文由自动测试系统(Automatic Test System,ATS)开发和SRAM(静态随机读写存储器)内建测试方法研究两部分组成。首先,电子控制系统是某型号大型电子装备的核心控制部件,有必要对其进行全面的功能、性能检测和故障诊断等工作。目前普遍采用内建测试(Built in Test,BIT)技术和自动测试(Automatic Test,AT)技术开展电子产品的可测试性工作。然而,该技术面临故障检测率(FaultDetection Rate,FDR)低、故障虚警率(Fault Alarm Rate,FAR)高等问题,严重降低其诊断结果的可信度。因此,在第二部分进行了对SRAM内建测试方法的深入研究,从故障模型和测试算法研究与优化入手,改进测试算法使其能检测出更多的SRAM故障。除此之外,可测试性工作通常由各科研单位独立研制,缺乏统一性、规范性和通用性。因此,在充分考虑现状之后,本文开展以下研究工作:(1)以往的测试方法是根据硬件电路的可测试点建立测试项目,然而该方法不具有通用性且测试覆盖率较低。本文将电子控制系统划分为六大功能模块,并分析各功能模块的故障模型、BIT设计特点,为其建立内建测试项目。(2)在集成CPCI板卡的自动测试设备上开发自动测试系统上位机平台,以衡量BIT对电子产品故障诊断能力。同时,为了减少同类自动测试设备的开发周期、成本以及提高软件后期维修和维护便利性,开发类驱动接口层软件,分离了上层界面和底层驱动,此方法具有较好的可移植性。(3)针对故障检测率低的问题,本文将研究重心转移到存储器故障检测上。由于存储器成为SoC中极为重要的组成部分且存储器在SoC占据极高的面积比例,本文重点针对存储器之一的静态随机读写存储器(Static Random Access Memory,SRAM)故障模型及其测试算法进行深入研究,并针对每一种单一故障和耦合故障总结其最简测试算法,经过合并优化,然后推导出具有较高故障检测率的MarchC-SOF+算法。提高SRAM的故障检测率从而提高整个电子控制系统的故障检测率。(4)使用VerilogHDL语言对SRAM的测试电路进行硬件语言描述,同时引入片选信号电路和门控时钟逻辑电路用以降低芯片功耗,并在ISE和ISE ChipScope平台上进行理论仿真和实验验证,以验证该方法的可行性以及在故障检测率方面的改善。
[Abstract]:This paper consists of two parts: (Automatic Test System,ATS (automatic test system) development and SRAM (static random access memory) built-in test method. First of all, the electronic control system is the core control component of a large electronic equipment, it is necessary to carry on the comprehensive function, the performance detection and the fault diagnosis and so on to the electronic control system. At present, built-in testing (Built in Test,BIT) technology and automatic testing (Automatic Test,AT) technology are widely used to carry out the testability of electronic products. However, this technique faces the problems of low fault detection rate (FaultDetection Rate,FDR) and high false alarm rate (Fault Alarm Rate,FAR), which seriously reduces the reliability of its diagnosis results. Therefore, in the second part, in-depth study of SRAM built-in testing methods, from the fault model and test algorithm research and optimization, improved testing algorithm to detect more SRAM faults. In addition, testability work is usually developed independently by scientific research institutes, lacking unity, standardization and generality. Therefore, after taking full account of the present situation, this paper carries out the following research work: (1) the former test method is based on the hardware circuit testable point to establish the test project, however, this method is not universal and the test coverage is low. In this paper, the electronic control system is divided into six functional modules, and the fault model of each functional module and the characteristics of BIT design are analyzed. To establish the built-in test project, (2) to develop the upper computer platform of the automatic test system based on the integrated CPCI board to measure the ability of BIT to diagnose the fault of electronic products. At the same time, in order to reduce the development cycle, cost and improve the convenience of maintenance and maintenance of the same kind of automatic test equipment, the class driver interface layer software is developed, and the upper interface and the bottom driver are separated. This method has good portability. (3) in order to solve the problem of low fault detection rate, the research focus is shifted to memory fault detection. Because memory is a very important part of SoC and the memory occupies a very high area ratio in SoC, this paper focuses on the static random access memory (Static Random Access Memory,), which is one of the memory. SRAM) fault model and its test algorithm are studied deeply, and the simplest test algorithm is summarized for each single fault and coupling fault. After combining and optimizing, the MarchC-SOF algorithm with high fault detection rate is deduced. Improve the fault detection rate of SRAM and improve the fault detection rate of the whole electronic control system. (4) using Verilog HDL language to describe the test circuit of SRAM with hardware language. At the same time, chip-selected signal circuit and gated clock logic circuit are introduced to reduce the power consumption of the chip. Theoretical simulation and experimental verification are carried out on ISE and ISE ChipScope platforms to verify the feasibility of this method and the improvement of fault detection rate.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP273;TP274;TP333

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