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面向PACDSP CORE的多核调试控制器硬件设计与软件验证

发布时间:2019-03-30 22:53
【摘要】:随着集成电路设计和制造技术的发展,芯片设计内部的规模也不断的变大,性能要求也不断的提高,使得单核已经逐步被多核所逐渐取代,软件上的程序设计也从串行程序设计到多线程程序开发,,随之而来的问题是调试变得越来越复杂,另外芯片市场竞争也变得越来越激烈,面对上市时间的巨大压力,实现一个稳定、高效的系统需要有效的软硬件调试方法变得尤为重要,如何缩短调试时间、提高调试速度对缩短SOC芯片的上市时间取决定性的意义。 本论文的主要研究工作是面向PACDSP CORE的多核调试控制器硬件设计与软件验证进行研究。论文详细的介绍了该调试控制器的硬件和软件部分,首先对于硬件内部的各个模块进行了详细的介绍,及其内部电路是如何实现的也作了详细的说明;然后对软件部分的断点种类进行介绍,如何设置/移除,所用调试工具及其支援的命令集有一一进行描述。 本文的整个操作流程是从PC机上的gdb窗口输入能支援的命令开始,软件部分主要是对这些命令进行解析,解析完毕后,执行相对应的功能,然后通过调用USB驱动,按照USB协议将这些信息传送给probe上的CYPRESS公司CY7C68013A芯片,该芯片会解析USB数据,并将解析出的信息写到它的slaveFIFO,然后probe会处理将这些信息反映到JTAG_WRAP上,Probe再透过JTAG接口与PACDSP内部的EICE电路进行信息交换,从而达到调试PACDSP的目的。 本文的最后有介绍如何进行仿真调试,从硬件的连接到软件的调试都有一一进行说明,其中硬件部分所需要的两块电路板,其中一块为probe部分,另外一块为EICE部分(除了EICE外,内嵌有两颗PACDSP CORE),并有对软件部分如何使用进行说明。 硬件线路连接好后,在PC机上透过gdb窗口输入命令,对所支援的命令逐一进行调试,都能达到预期的效果。
[Abstract]:With the development of IC design and manufacturing technology, the internal scale of chip design is also increasing, and the performance requirements are constantly improved, so that single core has been gradually replaced by multi-core. Software programming also from serial programming to multi-thread program development, followed by the problem is that debugging becomes more and more complex, in addition, the chip market competition has become more and more fierce, facing the huge pressure of time to market, In order to achieve a stable and efficient system, it is very important to use effective hardware and software debugging methods. How to shorten debugging time and how to improve debugging speed are of great significance to shorten the time to market of SOC chips. The main research work of this thesis is the hardware design and software verification of PACDSP CORE-oriented multi-core debug controller. The hardware and software parts of the debugging controller are introduced in detail. Firstly, the modules inside the hardware are introduced in detail, and how to realize the internal circuit is also explained in detail. Then the types of breakpoints in the software part are introduced, how to set / remove, and the debugging tools used and the command sets supported are described one by one. The whole operation flow of this paper starts from the gdb window on the PC to input the commands that can be supported. In the software part, the commands are parsed. After the parsing, the corresponding functions are executed, and then the USB driver is used. According to the USB protocol, this information is transmitted to the CYPRESS company CY7C68013A chip on the probe, which parses the USB data, writes the parsed information to its slaveFIFO, and probe processes the information to reflect the information on the JTAG_WRAP. Probe exchanges information with EICE circuit in PACDSP through JTAG interface, so as to debug PACDSP. At the end of this paper, we introduce how to do simulation debugging. From hardware connection to software debugging, there are two circuit boards, one of which is probe and the other is EICE (except EICE). Embedded with two PACDSP CORE), and instructions on how to use the software section. After the hardware circuit is connected, the commands can be inputted through the gdb window on PC, and the supported commands can be debugged one by one, which can achieve the desired effect.
【学位授予单位】:电子科技大学
【学位级别】:硕士
【学位授予年份】:2013
【分类号】:TP332

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