高速数传基带板及串行接口的设计
发布时间：2019-06-29 08:50
【摘要】：随着嵌入式处理技术的快速发展和人们对信息高速实时性的进一步要求，给高性能嵌入式系统带来了许多难题。在传统的嵌入式系统中，提高处理器的速度能极大改善系统性能。但研究表明，总线频率表征的CPU可用带宽的增长相对于由时钟频率表征的CPU内核性能的增长较慢，而且他们之间的差距正在逐步扩大。因此，提高处理器的处理速度对于系统性能提高的影响已经很微弱了，而系统内部不同模块之间的通信速度已成为了限制高速嵌入式系统性能提高的重要因素。于是，为了解决以上的难题，同时满足现在和未来高性能嵌入式系统需求，一种针对高性能嵌入式系统芯片间和板间互联而设计的，可实现点对点操作、高效且具有很高可靠性和有效拥塞控制的高速互联协议——RapidIO应运而生。 针对嵌入式系统的需求以及传统互连方式的局限性，RapidIO协议做了如下改进：提高打包效率，减小传输时延、简化流控机制和协议，限制软件复杂度，使得纠错重传机制乃至整个协议栈易于实现、支持多种速率传输模式和多种物理层技术，灵活且易于扩展等。 本文正是基于高性能嵌入式系统所面临的高速互联瓶颈以及RapidIO所体现出的优越性，对RapidIO技术进行分析和研究工作，具体如下：首先，对串行RapidIO协议的研究背景以及现阶段国内外的发展状况做简要说明。其次，就RapidIO协议结构进行深入研究。为了满足灵活性和可扩展性的要求，RapidIO协议分为三层：逻辑层、传输层和物理层，这种层次结构的最大特点是，修改任意层的事务类型都不会影响到其它层，紧接着说明搭建高速数传基带开发板平台。最后，在这个硬件平台上针对RapidIO协议，分别从端口的初始化、流量控制、错误管理等方面进行设计，实现FPGA芯片和DSP芯片间的高速串行互联，说明RapidIO协议在现今高速数传系统中的应用并进行仿真验证。通过理论分析和实验结果可以看出，，相对于其他的互联架构，RapidIO在功能、性能等方面具有明显的优势，是嵌入式系统互联的最佳选择之一。
[Abstract]:With the rapid development of embedded processing technology and the further requirements for high-speed real-time information, there are many problems for high-performance embedded systems. In the traditional embedded system, improving the speed of the processor can greatly improve the system performance. However, the research shows that the increase of available bandwidth of CPU represented by bus frequency is slower than that of CPU kernel characterized by clock frequency, and the gap between them is gradually widening. Therefore, the influence of improving the processing speed of the processor on the performance of the system is very weak, and the communication speed between different modules in the system has become an important factor limiting the performance improvement of the high-speed embedded system. Therefore, in order to solve the above problems and meet the needs of current and future high-performance embedded systems, a high-speed interconnection protocol, RapidIO, which can realize point-to-point operation and has high reliability and effective congestion control, is designed for the interconnection between chips and boards of high-performance embedded systems. In view of the requirements of embedded systems and the limitations of traditional interconnection methods, RapidIO protocol has made the following improvements: improving packaging efficiency, reducing transmission delay, simplifying flow control mechanism and protocol, limiting software complexity, making error correction retransmission mechanism and even the whole protocol stack easy to implement, supporting a variety of rate transmission modes and a variety of physical layer technologies, flexible and easy to expand, and so on. Based on the bottleneck of high-speed interconnection faced by high-performance embedded systems and the advantages of RapidIO, this paper analyzes and studies RapidIO technology as follows: firstly, the research background of serial RapidIO protocol and the development of serial RapidIO protocol at home and abroad are briefly described. Secondly, the structure of RapidIO protocol is deeply studied. In order to meet the requirements of flexibility and scalability, RapidIO protocol is divided into three layers: logic layer, transport layer and physical layer. the biggest characteristic of this hierarchical structure is that modifying the transaction type of any layer will not affect other layers, and then explains the construction of high-speed data transmission baseband development board platform. Finally, on this hardware platform, the RapidIO protocol is designed from the aspects of port initialization, flow control, error management and so on, and the high-speed serial interconnection between FPGA chip and DSP chip is realized. The application of RapidIO protocol in today's high-speed data transmission system is illustrated and verified by simulation. Through theoretical analysis and experimental results, it can be seen that RapidIO has obvious advantages in function and performance compared with other interconnection architecture, and it is one of the best options for embedded system interconnection.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7
本文编号：2507698
[Abstract]:With the rapid development of embedded processing technology and the further requirements for high-speed real-time information, there are many problems for high-performance embedded systems. In the traditional embedded system, improving the speed of the processor can greatly improve the system performance. However, the research shows that the increase of available bandwidth of CPU represented by bus frequency is slower than that of CPU kernel characterized by clock frequency, and the gap between them is gradually widening. Therefore, the influence of improving the processing speed of the processor on the performance of the system is very weak, and the communication speed between different modules in the system has become an important factor limiting the performance improvement of the high-speed embedded system. Therefore, in order to solve the above problems and meet the needs of current and future high-performance embedded systems, a high-speed interconnection protocol, RapidIO, which can realize point-to-point operation and has high reliability and effective congestion control, is designed for the interconnection between chips and boards of high-performance embedded systems. In view of the requirements of embedded systems and the limitations of traditional interconnection methods, RapidIO protocol has made the following improvements: improving packaging efficiency, reducing transmission delay, simplifying flow control mechanism and protocol, limiting software complexity, making error correction retransmission mechanism and even the whole protocol stack easy to implement, supporting a variety of rate transmission modes and a variety of physical layer technologies, flexible and easy to expand, and so on. Based on the bottleneck of high-speed interconnection faced by high-performance embedded systems and the advantages of RapidIO, this paper analyzes and studies RapidIO technology as follows: firstly, the research background of serial RapidIO protocol and the development of serial RapidIO protocol at home and abroad are briefly described. Secondly, the structure of RapidIO protocol is deeply studied. In order to meet the requirements of flexibility and scalability, RapidIO protocol is divided into three layers: logic layer, transport layer and physical layer. the biggest characteristic of this hierarchical structure is that modifying the transaction type of any layer will not affect other layers, and then explains the construction of high-speed data transmission baseband development board platform. Finally, on this hardware platform, the RapidIO protocol is designed from the aspects of port initialization, flow control, error management and so on, and the high-speed serial interconnection between FPGA chip and DSP chip is realized. The application of RapidIO protocol in today's high-speed data transmission system is illustrated and verified by simulation. Through theoretical analysis and experimental results, it can be seen that RapidIO has obvious advantages in function and performance compared with other interconnection architecture, and it is one of the best options for embedded system interconnection.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP334.7
【参考文献】
相关期刊论文 前2条
1 李宥谋;;8B/10B编码器的设计及实现[J];电讯技术;2005年06期
2 崔维嘉,樊少杰;新一代的总线结构──RapidIO[J];通信技术;2001年04期
本文编号：2507698
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2507698.html
