纳米级工艺下SRAM结构研究
发布时间：2019-07-05 10:55
【摘要】：静态随机存储器(SRAM)作为最重要的存储器之一,是现代SoC中关键部分,其功耗及稳定性等各方面性能是整个芯片性能的关键因素。半导体工艺进入纳米级以后,参数波动越来越大,漏电流功耗也越来越大,使得SRAM的设计在稳定性、功耗等方面面临新的问题。 论文通过分析纳米级工艺下集成电路设计面临功耗及稳定性方面的问题,进而对SRAM单元的功耗、稳定性等方面进行了深入的研究与分析。介绍SRAM单元电路中降低功耗的门控电源机制、晶体管堆叠机制、体偏置效应及使用FinFET晶体管方法的应用并比较其结果,并介绍分析SRAM结构稳定性的指标静态噪声容限,增强单元电路稳定性的动态电源机制以及几种提高稳定性的SRAM单元结构。论文分析了SRAM中动态功耗与静态功耗的来源并通过仿真分析其大小,同时还分析了结构中噪声的来源,介绍了蒙特卡罗分析法,并通过2000次蒙特卡罗仿真分析了噪声对SRAM结构读静态噪声容限的影响。 论文通过对SRAM单元功耗、噪声来源及改进思路的研究,进行了结构上的重新设计,并在此基础上提出了一种新型的单端读不对称8晶体管SRAM单元结构。继而详细介绍了该新结构的组成及工作原理,分析其功耗及噪声来源。最后对比标准6晶体管SRAM单元各方面的性能,对新8晶体管单元的功耗及稳定性进行评估。 本文在提出的新结构基础上通过辅以门控电源技术、亚阈值电压机制、动态电源法以及使用双栅结构晶体管来进一步提高其功耗、稳定性方面的性能,并比较结果。
[Abstract]:As one of the most important memory, static random access memory (SRAM) is a key part of modern SoC. Its power consumption and stability are the key factors of the whole chip performance. After the semiconductor process enters the nanometer level, the parameters fluctuate more and more, and the leakage current power consumption is also more and more large, which makes the design of SRAM face new problems in stability, power consumption and so on. In this paper, the power consumption and stability of integrated circuit design in nanometer process are analyzed, and then the power consumption and stability of SRAM unit are deeply studied and analyzed. This paper introduces the gated power supply mechanism, transistor stacking mechanism, volume bias effect and the application of FinFET transistor method in SRAM cell circuits, and compares the results, and introduces the static noise tolerance of SRAM structure stability, the dynamic power supply mechanism to enhance the stability of cell circuits and several SRAM cell structures to improve the stability. In this paper, the sources of dynamic power consumption and static power consumption in SRAM are analyzed and their magnitude is analyzed by simulation. At the same time, the source of noise in the structure is analyzed, the Monte Carlo analysis method is introduced, and the influence of noise on the reading static noise tolerance of SRAM structure is analyzed by 2000 Monte Carlo simulations. In this paper, the power consumption, noise source and improvement of SRAM unit are studied, and a new single-terminal read asymmetrical 8-transistor SRAM cell structure is proposed. Then the composition and working principle of the new structure are introduced in detail, and its power consumption and noise source are analyzed. Finally, the power consumption and stability of the new 8 transistor cell are evaluated by comparing the performance of the standard 6 transistor SRAM cell. In this paper, the proposed new structure is supplemented by gated power supply technology, subthreshold voltage mechanism, dynamic power supply method and the use of double-gate transistors to further improve its power consumption and stability performance, and compare the results.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333.8
本文编号：2510467
[Abstract]:As one of the most important memory, static random access memory (SRAM) is a key part of modern SoC. Its power consumption and stability are the key factors of the whole chip performance. After the semiconductor process enters the nanometer level, the parameters fluctuate more and more, and the leakage current power consumption is also more and more large, which makes the design of SRAM face new problems in stability, power consumption and so on. In this paper, the power consumption and stability of integrated circuit design in nanometer process are analyzed, and then the power consumption and stability of SRAM unit are deeply studied and analyzed. This paper introduces the gated power supply mechanism, transistor stacking mechanism, volume bias effect and the application of FinFET transistor method in SRAM cell circuits, and compares the results, and introduces the static noise tolerance of SRAM structure stability, the dynamic power supply mechanism to enhance the stability of cell circuits and several SRAM cell structures to improve the stability. In this paper, the sources of dynamic power consumption and static power consumption in SRAM are analyzed and their magnitude is analyzed by simulation. At the same time, the source of noise in the structure is analyzed, the Monte Carlo analysis method is introduced, and the influence of noise on the reading static noise tolerance of SRAM structure is analyzed by 2000 Monte Carlo simulations. In this paper, the power consumption, noise source and improvement of SRAM unit are studied, and a new single-terminal read asymmetrical 8-transistor SRAM cell structure is proposed. Then the composition and working principle of the new structure are introduced in detail, and its power consumption and noise source are analyzed. Finally, the power consumption and stability of the new 8 transistor cell are evaluated by comparing the performance of the standard 6 transistor SRAM cell. In this paper, the proposed new structure is supplemented by gated power supply technology, subthreshold voltage mechanism, dynamic power supply method and the use of double-gate transistors to further improve its power consumption and stability performance, and compare the results.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP333.8
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