低消耗免查找表CORDIC算法

发布时间：2019-06-14 04:51

【摘要】：为减少传统流水线型CORDIC(Coordinate Rotation Digital Computer)算法的硬件资源消耗和输出时延,在包含查找表的三阶段CORDIC算法实现基础上,提出一种免去查找表环节的CORDIC算法实现方法.提出的改进算法直接使用四次移位相加的迭代运算替换查找表结构从而显著降低寄存器消耗,同时通过合并迭代降低迭代次数进而有效减少最大输出时延,并综合运用角度二极化重编码(Binary To Bipolar Recoding,BBR)方法和角度区间折叠技术保证了输出精度.使用Verilog HDL语言在ISE14.2软件平台上对三种算法进行具体实现,利用XST工具对其进行综合,并通过MATLAB建模计算得到算法的正余弦值输出误差.仿真实验结果表明:在输出位宽均设置为16位的情况下,免查找表CORDIC算法能够有效地输出正余弦值;与传统流水线型算法相比,免查找表算法的寄存器资源消耗减少大约74.42%,计算所需的时钟周期降低68.75%,其输出精度也有明显改善;与三阶段算法相比,免查找表算法的寄存器消耗减少大约43.3%.本文提出的免查找表CORDIC算法具有实时性强、输出精度高、硬件资源消耗少等优势,更适用于高速实时的现代数字通信系统应用.
[Abstract]:In order to reduce the hardware resource consumption and output delay of traditional streamline CORDIC (Coordinate Rotation Digital Computer) algorithm, a CORDIC algorithm implementation method without look-up table link is proposed on the basis of the implementation of three-stage CORDIC algorithm including look-up table. The improved algorithm directly uses the iterative operation of four shifts to replace the look-up table structure, thus significantly reducing register consumption, and effectively reduces the maximum output delay by combining iterations to reduce the number of iterations, and combines the angle polarization recoding (Binary To Bipolar Recoding,BBR) method and the angle interval folding technique to ensure the output accuracy. Verilog HDL language is used to implement the three algorithms on ISE14.2 software platform, and XST tools are used to synthesize them, and the sine and cosine output error of the algorithm is obtained by MATLAB modeling and calculation. The simulation results show that the CORDIC algorithm can effectively output the sine and cosine values when the output bit width is set to 16 bits, and compared with the traditional streamline algorithm, the register resource consumption of the table-free algorithm is reduced by about 74.42%, the clock cycle required by the calculation is reduced by 68.75%, and the output accuracy is obviously improved. Compared with the three-stage algorithm, the register consumption of the table-free algorithm is reduced by about 43.3%. The CORDIC algorithm proposed in this paper has the advantages of strong real-time performance, high output accuracy and low consumption of hardware resources, so it is more suitable for the application of high-speed and real-time modern digital communication system.
【作者单位】：中国地质大学(武汉)机械与电子信息学院;
【基金】：国家自然科学基金(61601334)
【分类号】：TP301.6

【相似文献】