H.264视频众核解码研究及在定制众核虚拟平台上的实现

发布时间：2018-07-17 08:25

【摘要】：视频编解码技术在数字高清电视、网络流媒体、视频通信等领域广泛应用,目前主流的标准是2003.3正式发布的H.264/AVC与2013.1正式发布的HEVC/H.265。现存大量H.264标准的视频文件,且相较HEVC, H.264的解码算法复杂度更低一些,本文选择H.264众核解码做为研究起点。H.264标准为保证高画质、低码率,需要进行大量的计算,目前H.264解码方案主要有高性能CPU/DSP方案、硬件加速专用模块、专用ASIC芯片/FPGA方案、多核(2/4核、ARM+DSP结构)方案,各方案在性能、功耗、灵活性方面各有优缺点。本文面向H.264视频解码应用,研究高性能、低功耗、高灵活性的H.264视频众核(16核及以上)解码实现方案,探索解决H.264众核解码中的关键技术问题,所得结果亦可用于H.265及其他视频标准。目标众核平台是由MCVP-NoC系统构建生成的虚拟平台。MCVP-NoC是自行设计的支持定制NoC (Networks-on-Chip,片上网络)的多核虚拟平台建模工具,它采用“SystemC + TLM2.0 + OVP”工具构建,MCVP-NoC生成的虚拟平台能运行实际程序,支持真实应用驱动,可用于项目早期软件开发、调试,系统架构探索,以及性能、功耗、面积评估等。本文的主要工作有:(1)分析H.264解码计算性能瓶颈;(2) H.264解码的任务划分与众核映射。先按解码流程进行任务划分,采用“码流分析、slice解码、滤波、输出”四级流水,再对解码流程各部分按计算量划分,进行多核并行加速。(3)构建众核虚拟平台,用其运行H.264众核解码程序,评测性能。众核系统采用4x4 2D mesh结构,共16个处理器节点,每个节点含1个orlk处理器、32M字节指令存储器、32M字节数据存储器,所有节点共享1个256M字节shared-memory。该模型可运行实际H.264解码代码,能定量分析性能,可用于系统架构优化、片上存储需求分析,存储方案优化;能定量分析核间通信流量,可用于指导核间NoC互联结构与链路带宽设计。
[Abstract]:Video coding and decoding technology is widely used in digital HDTV, network streaming media, video communication and so on. At present, the main standard is H.264 / AVC which was officially released in 2003.3 and HEVC / H.265which was officially released in 2013.1. There are a large number of H.264 standard video files, and the complexity of H.264 decoding algorithm is lower than that of HEVC, H.264 decoding is chosen as the research starting point. H.264 standard is used to guarantee high quality and low bit-rate, it needs a lot of calculation. At present, H.264 decoding schemes mainly have high performance CPU / DSP scheme, special hardware acceleration module, ASIC chip / FPGA scheme and multi-core (2 / 4 core arm DSP structure) scheme. Each scheme has its own advantages and disadvantages in performance, power consumption and flexibility. For H.264 video decoding applications, this paper studies the implementation scheme of H.264 video multi-core (16 cores and above) with high performance, low power consumption and high flexibility, and explores the key technical problems in H.264 video decoding. The results can also be used in H. 265 and other video standards. The target multi-core platform is a virtual platform built by MCVP-NoC system. MCVP-NoC is a multi-core virtual platform modeling tool designed by itself to support customized Noc (Networks-on-Chip). It uses "system C TLM2.0 OVP" tool to build virtual platform generated by MCVP-NoC, which can run actual program, support real application driver, and can be used in early software development, debugging, system architecture exploration, performance, power consumption, area evaluation and so on. The main work of this paper is as follows: (1) analyzing the bottleneck of H. 264 decoding computing performance; (2) mapping the task partition of H. 264 decoding and the map-core. First, the task is divided according to the decoding flow, and then the multi-core parallel acceleration is carried out according to the calculation amount of each part of the decoding process, and the "stream analysis slice decoding, filtering, output" four-level pipeline is adopted. (3) the multi-core virtual platform is constructed, and the multi-core virtual platform is constructed. Use it to run H.264 core decoding program to evaluate the performance. The multi-core system uses 4x4 2D mesh structure, 16 processor nodes, each node contains one orlk processor 32m byte instruction memory 32 megabyte data memory, all nodes share a 256m byte shared-memory. The model can run actual H.264 decoding code, can quantitatively analyze performance, can be used for system architecture optimization, on-chip storage requirement analysis, storage scheme optimization, and quantitative analysis of inter-core communication traffic. It can be used to guide the design of NOC interconnection structure and link bandwidth between cores.
【学位授予单位】：山东科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN919.81

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