时间触发以太网容错时钟同步机制的研究与硬件实现

发布时间：2018-01-05 21:32

本文关键词：时间触发以太网容错时钟同步机制的研究与硬件实现　出处：《北京交通大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着现代电子系统功能越来越丰富,集成模块越来越复杂,对网络带宽、延迟、可靠性等指标提出了更高的要求。实时性以太网作为未来以太网的发展方向,而时间触发以太网(TTE)相比于其他网络技术,具备了与传统以太网的兼容性,成为最具发展前景的项目之一。特别是满足了工业级以太网以及国防、航天领域对强实时性,高可靠性的需求,使得该技术越来越具备发展潜力。本文为寻求一种强实时,高带宽,高可靠性网络传输技术,进行相关理论研究和算法设计实现,研究内容如下:(1)对TTP/C、FlexRay、TTE进行研究比较,由于TTE对传统以太网有较好的兼容性,且具有较高的时钟精度与容错性能,便将TTE作为本文的研究对象。(2)本文就TTE的AS6802协议进行研究,深入理解网络中不同数据帧的分发调度原理;掌握TTE同步操作中的时间固化算法与压缩算法;分析网络中关节节点SM、CM、SC的功能,各个节点的状态机的状态所对应的操作以及状态转移条件;深入分析TTE的容错机制以及团检测机制的容错方法。(3)根据以上研究,在OPNET上完成对TTE容错时钟同步机制的设计。建立终端节点与交换机的节点模型,设计SM、CM、SC状态机进程模型,根据不同仿真场景完成对TTE同步机制的测试与验证;通过设置故障节点参数,完成对TTE容错机制的测试与验证。(4)对SM节点进行硬件模块设计,实现相应的功能,并利用Modelsim进行关键模块的功能仿真。根据测试结果显示,TTE容错时钟同步机制是一套完备的时钟同步与设备容错的解决方案,各方面性能均达到预期结果,同步精度高,容错性能强。
[Abstract]:With the development of modern electronic systems are more and more rich, more and more complex integrated module of network bandwidth, delay, and put forward higher requirements of reliability. The real-time Ethernet as the future direction of development of Ethernet, and time triggered Ethernet (TTE) compared to other network technology, and has become one of the traditional Ethernet Compatibility. The project has the most development prospect. Especially to meet the industrial Ethernet and the field of aerospace defense, strong real-time, high reliability requirements, making the technology more and more have development potential. This paper is to seek a strong real-time, high bandwidth, high reliability of network transmission technology, to achieve the relevant theoretical research and algorithm design. The research contents are as follows: (1) on TTP/C, FlexRay and TTE were compared, because the TTE has good compatibility with the traditional Ethernet, and has the clock precision and high fault tolerance performance, Will TTE as the research object of this paper. (2) this paper studies the TTE protocol of AS6802, understanding the dispatch principle of different data frames in the network; the time synchronization operation in curing TTE algorithm and compression algorithm; analysis of joint network node SM, CM, SC function, the corresponding state machine the state of each node operation and state transition conditions; fault tolerant method to analyze fault tolerance mechanisms of TTE and cluster detection mechanism. (3) according to the above research, the design of TTE fault-tolerant clock synchronization mechanism in OPNET. The node model, establish the terminal nodes and switches SM, CM, SC state machine process the model, according to the different simulation scenarios to complete the test and verification of TTE synchronization mechanism; fault by setting the node parameters, complete the test and verification of fault tolerance mechanism for TTE. (4) the hardware module design of SM node, the realization of the corresponding function Modelsim is used to perform the functional simulation of the key modules. According to the test results, the TTE fault tolerant clock synchronization mechanism is a complete solution for clock synchronization and device fault tolerance. All aspects of the performance achieve the expected results, the synchronization accuracy is high, and the fault tolerance is strong.

【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP393.11

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