倍频延迟锁定环的研究与设计

发布时间：2018-04-08 11:38

本文选题：时钟倍频　切入点：锁相环　出处：《北京交通大学》2017年硕士论文

【摘要】：锁相技术在无线收发器、传输接口、微处理器等领域,有着广泛的应用。包括锁相环(Phase-Locked Loop)、串行/解串器(SerDes)、时钟与数据恢复(Clock andDataRecovery)电路在内的一系列电路的设计一直是国内外各高校、研究机构以及企业研究的热点。近年来,随着物联网技术以及半导体技术的快速发展,各种微处理器的运算能力越来越强,数字设备之间的数据交换速度越来越快,如何在提高速度的同时保障数据传输的可靠性,是一个值得研究的问题。在许多应用中,高速串行接口已经逐渐取代了传统的并行接口。在高速串行通信接口中常常使用锁相环来产生高频率的时钟信号,但锁相环本身的抖动积累问题增加了输出时钟上的抖动,限制了数据传输的速度。延迟锁定环(Delay-Locked Loop)具有比锁相环更好的抖动性能,因此在一些对时钟抖动性能要求更高的应用中,延迟锁定环通常是一个更好的选择,但因其无法像锁相环那样灵活地实现频率倍增的功能,它的应用受到了一定的限制。本文在对锁相环、延迟锁定环这两种常见锁相电路进行分析与比较的基础上,介绍了一种将二者优势相结合的新型锁相技术——倍频延迟锁定环(Multiplying Delay-Locked Loop),它克服了传统锁相环电路存在抖动积累的问题,同时保留了其能够灵活实现倍频的特性。随后,本文对一种倍频延迟锁定环电路的工作原理和结构进行了详细地分析,给出了 0.18μm标准CMOS工艺下整体电路从原理图到版图的设计,所设计的倍频延迟锁定环的倍频比为7,可捕获的输入参考频率范围为 25MHz 到 100MHz。本文的最后,给出了电路的仿真结果。仿真结果表明,当工艺参数、电源电压、温度在一定范围内变化时,所设计的MDLL电路均能稳定工作。当输入100MHz的参考时钟信号时,输出时钟频率为700MHz,抖动的峰峰值小于26ps。
[Abstract]:Phase-locked technology has been widely used in wireless transceiver, transmission interface, microprocessor and other fields.The design of a series of circuits including phase-locked loop Phase-Locked Looper serial / demultiplexer SerDesan clock and data recovery circuits has always been a hot research topic in universities research institutions and enterprises at home and abroad.In recent years, with the rapid development of the Internet of things technology and semiconductor technology, the computing power of various microprocessors is becoming stronger and stronger, and the speed of data exchange between digital devices is becoming faster and faster.How to improve the speed and ensure the reliability of data transmission is a problem worth studying.In many applications, high-speed serial interface has gradually replaced the traditional parallel interface.Phase locked loop (PLL) is often used to generate high frequency clock signal in high speed serial communication interface, but the jitter accumulation of PLL itself increases the jitter on the output clock and limits the speed of data transmission.Delay locking loop (Delay-Locked Loop) has better jitter performance than phase-locked loop (PLL), so it is usually a better choice in some applications with higher clock jitter performance.However, its application is limited because it can not realize the function of frequency multiplication as flexibly as PLL.Based on the analysis and comparison of two common phase-locked circuits, the phase-locked loop and the delay-locked loop are analyzed and compared in this paper.This paper introduces a new phase-locking technique, frequency-doubling Delay-Locked locking loop, which combines the advantages of the two techniques. It overcomes the problem of jitter accumulation in the traditional PLL circuit and retains the characteristic that it can realize frequency doubling flexibly.Then, the working principle and structure of a frequency-doubling delay locking loop circuit are analyzed in detail, and the design of the whole circuit from schematic to layout in 0.18 渭 m standard CMOS process is given.The designed double frequency delay locking loop has a frequency doubling ratio of 7 and a trapping reference frequency range of 25MHz to 100 MHz.Finally, the simulation results of the circuit are given.The simulation results show that the designed MDLL circuit can work stably when the process parameters, power supply voltage and temperature change in a certain range.When the reference clock signal of 100MHz is input, the output clock frequency is 700MHz and the peak value of jitter is less than 26ps.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN911.8

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