多模CMOS频率综合器关键模块设计及其整体优化

发布时间：2018-04-14 14:22

  本文选题：多模多标准 + 小数频率综合器　； 参考：《东南大学》2017年硕士论文

【摘要】：随着无线通信模式的不断涌现,将多种通信制式集成在一个移动终端上已成为目前无线通信技术发展的趋势,支持多模式、多标准、多频段的射频收发机也因此成为人们研究的热点。而作为射频收发机的核心组成模块之一,频率综合器是决定整个收发机性能的关键之一。本文对多模CMOS频率综合器关键模块及其整体优化进行研究与设计。本文首先介绍了电荷泵锁相环型小数频率综合器的基本原理和各个子模块,推导出系统传递函数并建立线性化模型,然后根据其线性化模型分析了环路的稳定性、动态特性和噪声性能,并给出了小数频率综合器的系统结构框图。本文设计的小数分频器主要包括高速二分频器、可编程整数分频器和Δ-Σ调制器。高速二分频器采用源级耦合逻辑结构的触发器实现,在进行二分频功能的同时产生四相正交本振信号。可编程整数分频器包括四分频器和2/3分频器链,其中2/3分频器链采用5级2/3分频器级联而成,并加入逻辑门实现分频比的扩展。A-Σ调制器用于实现量化噪声的整形,采用了改进型MASH 1-1-1结构,可以增加输出序列长度以减小小数杂散。本文设计的自动频率校准单元(AFC)基于频率比较法,主要包括最优控制字搜索模块和环路带宽校准模块。最优控制字搜索利用二进制搜索算法和最小值存储来实现,环路带宽校准则根据当前分频比和压控振荡器的调谐增益来调节电荷泵电流,以实现环路带宽的恒定。基于混合型FIR滤波的量化噪声抑制技术,本文对小数频率综合器进行了系统优化设计。A-Σ调制器的输出控制信号经过延迟单元后,分别通过8路并行的可编程整数分频器和鉴频鉴相器,最后由一个8输入可编程电荷泵在模拟域进行电荷相加。混合型FIR滤波器能够实现全定制的量化噪声整形,并且恒定的单位直流增益避免了噪声放大的问题。基于TSMC 0.18μm RF CMOS工艺进行了电路设计和版图设计,整个小数频率综合器的版图面积为1.22x1.07mm2。其中A-∑调制器和自动频率校准单元采用半定制设计方法,其余模块均采用全定制设计方法。后仿真结果表明,在最差情况下小数分频器的工作范围为0.4～8.0GHz,分频比范围为32～504,最高频率下的工作电流为7.65mA。自动频率校准单元的校准时间约为16.2μs,频率分辨率为5MHz,平均工作电流小于0.5mA。整个小数频率综合器的仿真结果表明,输出频率范围为0.923～7.681GHz,频率分辨率为20Hz,锁定时间小于40μs,工作电流小于23mA。本次设计的小数频率综合器能够满足设计指标要求。
[Abstract]:With the continuous emergence of wireless communication modes, it has become the trend of wireless communication technology to integrate multiple communication systems on one mobile terminal, which supports multi-mode and multi-standard.Therefore, RF transceiver in multi-frequency band has become a hot research topic.As one of the core modules of RF transceiver, frequency synthesizer is one of the key factors to determine the performance of the whole transceiver.In this paper, the key modules and their overall optimization of multimode CMOS frequency synthesizer are studied and designed.In this paper, the basic principle and sub-modules of the charge pump phase-locked loop fractional frequency synthesizer are introduced, the system transfer function is derived and the linearization model is established, and then the stability of the loop is analyzed according to the linearization model.The system structure block diagram of fractional frequency synthesizer is given.The fractional divider designed in this paper mainly includes high speed dicusser, programmable integer divider and 螖-危 modulator.The high speed frequency divider is realized by the trigger with the source level coupling logic structure. The quadrature local oscillator signal is generated while the frequency division function is carried out.The programmable integer frequency divider consists of four frequency dividers and a 2 / 3 frequency divider chain, in which the 2 / 3 frequency divider chain is cascaded by a 5 stage 2 / 3 frequency divider, and an expanded. A- 危 modulator to realize the division ratio is added to realize the shaping of the quantization noise.The improved MASH 1-1-1 structure can increase the output sequence length to reduce the fractional spurious.The automatic frequency calibration unit (AFC) designed in this paper is based on the frequency comparison method, including the optimal control word search module and the loop bandwidth calibration module.The optimal control word search is realized by binary search algorithm and the minimum storage. The loop bandwidth calibration is based on the current frequency division ratio and the tuning gain of the voltage controlled oscillator to adjust the charge pump current to realize the constant bandwidth of the loop.Based on the quantization noise suppression technique of hybrid FIR filter, the output control signal of the fractional frequency synthesizer is optimized by the delay unit after the output control signal of the .A- 危 modulator is optimized.Through 8 parallel programmable integer dividers and phase discriminators, an 8-input programmable charge pump is used to add charges in analog domain.The hybrid FIR filter can realize fully customized quantization noise shaping, and the constant unit DC gain avoids the problem of noise amplification.The circuit design and layout design based on TSMC 0.18 渭 m RF CMOS process are carried out. The layout area of the whole decimal frequency synthesizer is 1.22 x 1.07mm 2.The A- 鈭，

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