小型化低相位噪声取样锁相SIW振荡器

发布时间：2018-06-20 08:29

本文选题：基片集成波导压控振荡器 + 基片集成波导谐振器　；参考：《东南大学》2017年硕士论文

【摘要】：现代雷达和导引系统要求发射信号具有低相位噪声和高频率稳定度,这对本振信号源的技术指标和小型化提出了极高要求。随着晶体振荡器技术的高速发展,现在我们很容易获得频率稳定度极高、相位噪声优异、杂散电平良好的参考频率源。但如何简洁、高效、稳定的利用这些参考源设计微波锁相振荡源则是微波电路设计中面临的挑战。传统锁相源(PLL)通常采用数字锁相环、倍频链、取样锁相DRO等较成熟的电路形式来实现对参考源的跟踪和扩展。数字锁相环电路简化好集成,但性能不够好;倍频链近端相噪好,但集成度低、底噪高;模拟取样锁相DRO能够性能最好,但是由于DRO电路和取样环路较复杂很难小型化。本论文对传统取样方案进行改进,采用集成度更高的基片集成波导压控振荡器(SIWVC O)代替介质压控振荡器(DRVCO),并结合多层PCB工艺和MCM技术减小取样环路尺寸。论文首先讨论了 SIWVCO设计原理和电路形式,采用电路模型仿真结合电磁场仿真的方案对SIWVCO电路进行仿真和优化,设计的SIWVCO集成度高、相位噪声低;然后分析取样锁相源工作原理,采用多层PCB工艺结合MCM技术的方案设计了取样电路。最后测试结果为在载波 12GHz 相位噪声分别为-110dBc/Hz@lKHz,-120dBc/Hz@10KHz,-116dBc/Hz@100KHz,-130dBc/Hz@1MHz。
[Abstract]:Modern radar and guidance systems require low phase noise and high frequency stability of the transmitted signal, which puts forward very high requirements for the technical specifications and miniaturization of the local oscillator signal source. With the rapid development of crystal oscillator technology, it is easy to obtain reference frequency sources with high frequency stability, excellent phase noise and good stray level. However, how to use these reference sources to design microwave phase-locked oscillators is a challenge in microwave circuit design. The traditional PLL (PLL) usually uses digital phase-locked loop, frequency-doubling chain, sampling phase-locked DRO and other mature circuit forms to track and expand the reference source. The digital PLL circuit simplifies and integrates well, but the performance is not good enough; the near-end phase noise of the frequency doubling chain is good, but the integration level is low and the bottom noise is high; the analog sampling phase-locked DRO circuit has the best performance, but it is difficult to miniaturize the DRO circuit and the sampling loop because of the complexity of the DRO circuit and the sampling loop. In this paper, the traditional sampling scheme is improved by using a more integrated substrate integrated waveguide voltage controlled oscillator (SIWVC O) instead of the dielectric voltage controlled oscillator (DRVCOO), and combining the multi-layer PCB process and MCM technology to reduce the size of the sampling loop. Firstly, the design principle and circuit form of SIWVCO are discussed. The scheme of circuit model simulation and electromagnetic field simulation is used to simulate and optimize SIWVCO circuit. The designed SIWVCO circuit has high integration and low phase noise. Then, the principle of sampling phase-locked source is analyzed, and the sampling circuit is designed by using multi-layer PCB technology and MCM technology. The final test results show that the phase noise at 12GHz is -110dBc / Hz-lKHz-120dBc / Hz-10kHz / 10kHz-116dBc / HzR @ 100kHz-130dBc / Hzfuture 1MHz.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN752

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