抗功耗分析攻击的高速ECC算法加速器

发布时间：2018-04-21 22:20

本文选题：椭圆曲线密码体制 + 点乘　；参考：《杭州电子科技大学》2014年硕士论文

【摘要】：随着信息安全需求的日益增长，目前普遍采用的1024位RSA算法面临严重的安全威胁，而ECC（椭圆曲线密码）算法相比RSA算法在安全性和加解密速率方面具有显著的优势，为了保障重要经济领域密码应用的安全，我国国家密码管理局制定了具有自主知识产权的ECC国家标准算法（即SM2算法），公布了相关标准及规范，并要求相关行业采用SM2算法替换RSA算法。同时，针对ECC算法的旁路攻击技术也是层出不穷，其中功耗分析攻击就是利用ECC在加解密过程中泄露的功耗信息进行攻击，这种攻击方法效率高，威胁性大。因此，ECC国家标准算法如何高速实现及其抗功耗分析攻击的研究成为当前及未来密码产业关注的热点。本文针对ECC的应用需求，设计了一款面向SOC设计的素数域上ECC加速器IP，结合ECC算法原理和硬件实现的特点，提出一种安全、高效、易实现的算法方案，用软件验证了方案的正确性和可行性后，采用verilog硬件描述语言完成ECC加速器的RTL设计，并通过详细的仿真验证及逻辑综合，验证了加速器的算法正确性、速度以及面积等性能指标。除此之外，本文针对加密算法搭建了功耗分析攻击平台，为验证ECC加速器抗功耗分析攻击的能力奠定了基础。本文实现的加速器支持192/256bit多种椭圆曲线的应用，支持固定基单基点乘和双点乘运算，其中双点乘运算中提出了从左到右联合编码和Shamir双点乘相结合的快速算法。加速器基于SMIC0.13um工艺和200MHz频率，，256bit素数域上每秒能完成5000次签名和1600次验证。这对于今后高性能的密码芯片产品研发有着重要的参考意义。
[Abstract]:With the increasing demand for information security, the widely used 1024 bit RSA algorithm is facing a serious security threat. Compared with the RSA algorithm, the ECC (elliptic curve cryptography) algorithm has significant advantages in terms of security and encryption and decryption rate. In order to ensure the security of cryptographic applications in important economic fields, the State Cryptography Administration of China has formulated the ECC national standard algorithm (SM2 algorithm) with independent intellectual property rights, and published the relevant standards and specifications. And requires the relevant industries to replace the RSA algorithm with the SM2 algorithm. At the same time, the bypass attack technology for ECC algorithm is emerging in endlessly, in which power analysis attack is to use the power information leaked in the process of encryption and decryption of ECC to attack. This attack method is highly efficient and threatening. Therefore, how to implement the ECC national standard algorithm at high speed and how to resist the power analysis attack has become a hot topic in the cryptographic industry at present and in the future. According to the application requirements of ECC, this paper designs a ECC accelerator for SOC design in prime number domain. Combining with the principle of ECC algorithm and the characteristics of hardware implementation, a safe, efficient and easy to implement algorithm scheme is proposed. After the correctness and feasibility of the scheme are verified by software, the RTL design of ECC accelerator is completed by using verilog hardware description language, and the algorithm of the accelerator is verified by detailed simulation and logic synthesis. Speed and area and other performance indicators. In addition, this paper builds a power analysis attack platform for encryption algorithm, which lays a foundation for verifying the ability of ECC accelerator to resist power analysis attack. The accelerator implemented in this paper supports the application of multiple elliptic curves of 192/256bit, and supports the fixed basis single base point multiplication and double point multiplication operations. In the double point multiplication operation, a fast algorithm combining left to right joint coding and Shamir double point multiplication is proposed. The accelerator can complete 5000 signatures and 1600 verifications per second based on the SMIC0.13um process and the 200MHz frequency of 256bit prime number domain. This is of great significance for the future research and development of high-performance cipher chip products.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN918.4

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