复杂多核系统的调试系统设计与研究

发布时间：2018-09-08 10:53

【摘要】：随着嵌入式系统与FPGA开发平台的深度融合,使得基于FPGA的片上可编程系统(System-on-a-Programmable-Chip,SOPC)技术得到了前所未有的蓬勃发展。以专用FPGA芯片为核心的开发平台,具有软硬件“量体裁衣”的灵活选择性和可编程特性,甚至可根据用户设计需求进行个性化定制,因此受到行业开发者们青睐。基于FPGA内嵌的可配置软核,以及可复用的知识产权(IntellectualProperty, IP),通过总线与外围硬件设备可实现微处理器技术、SOPC设计和软硬协同设计等,大大降低设计难度和缩短系统开发时间,提高资源复用率。然而,随着复杂多核SoC的设计复杂性的增加与性能的提升,使得软硬件调试任务越来越艰巨,传统的测试方法与调试手段无法在有限条件下保证芯片功能设计的正确性,而且在验证上花费的代价越来越高,要想一次性成功完成芯片设计显得越来越困难。因此,能够提高调试质量的多核调试技术是减少软硬件调试时间和降低设计成本的关键,SOPC技术的出现可以极大改变传统的调试方法,提高复杂多核SoC的调试效率。本文主要对基于NoC的复杂多核系统的调试技术进行了深入研究,基于SOPC技术思想设计并实现了一款实用的调试系统,论文主要工作与研究内容如下:首先,对当前调试技术和项目组设计的复杂多核系统进行了研究与分析,完成了目标系统的软件指令自刷新功能,在此基础上基于SOPC技术实现了一款具有可配置、可编程、可裁剪和可移植的调试系统架构,该架构能够完成对目标系统的关键数据信息追踪以及监测、任务调度和系统控制等,可以还原系统的工作流程,具有很好的实用价值,大大降低复杂多核SoC调试的时间,加快芯片设计进程。其次,对调试系统架构的各个关键模块设计进行了深入研究与分析,主要包括根据目标系统工作机制特点设计的调试结构、调试系统命令和数据的传输机制、调试系统的四种调试模式、调试系统的调试接口(DebugInterface,DI)模块以及相关的软硬件模块等,结合SOPC技术和软硬协同设计方法实现了具有一定的高效性、实用性以及可移植特性的调试系统,完成了针对目标系统的调试控制指令设计和相应的调试流程。最后,将本文设计与实现的调试系统集成到目标系统中,基于Virtex-6 XC6VLX760 FPGA开发板进行调试系统的输入输出器件的协作测试,在目标系统的测试任务集中,选取了经典的大点FFT卷积运算进行算法分析与映射,在目标系统中完成任务加载并进行调试系统的FPGA测试验证。实验结果表明,在不影响目标系统正常任务执行的情况下,通过友好的调试界面可以很好的完成关键数据信息监测、任务追踪和系统控制等调试需求,证明了本课题设计与实现的复杂多核系统的调试系统方案的可行性,该调试系统设计过程具有两大特色,即SOPC技术思想和软硬协同设计方法,并且满足复杂多核SoC的调试需求,具有一定的实际应用价值。
[Abstract]:With the deep integration of embedded system and FPGA development platform, the technology of system-on-a-Programmable-Chip (SOPC) based on FPGA has been flourishing unprecedentedly. Based on the configurable soft core embedded in the FPGA and the reusable intellectual property (IP), microprocessor technology, SOPC design and hardware-software co-design can be realized by bus and peripheral hardware devices, which greatly reduces the design difficulty and complexity. However, with the increase of complexity and performance of complex multi-core SoC design, the task of debugging software and hardware becomes more and more difficult. Traditional testing methods and debugging methods can not guarantee the correctness of chip function design under limited conditions, and the cost of verification increases. Therefore, the multi-core debugging technology which can improve the debugging quality is the key to reduce the debugging time and design cost. The appearance of SOPC technology can greatly change the traditional debugging methods and improve the debugging efficiency of complex multi-core SoC. The debugging technology of complex multi-core system based on NoC is deeply studied. A practical debugging system is designed and implemented based on SOPC technology. The main work and research contents of this paper are as follows: Firstly, the current debugging technology and the complex multi-core system designed by the project team are studied and analyzed, and the software finger of the target system is completed. Based on the SOPC technology, a debugging system architecture with configurable, programmable, tailorable and portable functions is implemented. The architecture can track and monitor the key data of the target system, schedule tasks and control the system, and restore the work flow of the system. It has a good practical price. Secondly, the design of the key modules of the debugging system architecture is deeply studied and analyzed, including the debugging structure designed according to the characteristics of the working mechanism of the target system, the transmission mechanism of the commands and data of the debugging system, and the four debugging mechanisms of the debugging system. The debugging system with high efficiency, practicability and portability is realized by combining SOPC technology with software and hardware co-design method. The debugging control instruction design and corresponding debugging process for the target system are completed. Then, the debugging system designed and implemented in this paper is integrated into the target system, and the input and output devices of the debugging system are tested cooperatively based on the Virtex-6XC6VLX760 FPGA development board. In the test task set of the target system, the classic large-point FFT convolution operation is selected for algorithm analysis and mapping, and the task addition is completed in the target system. The experimental results show that the debugging requirements such as key data information monitoring, task tracking and system control can be well fulfilled through a friendly debugging interface without affecting the normal task execution of the target system. The feasibility of the system scheme, the debugging system design process has two characteristics, namely, SOPC technology and hardware-software co-design method, and meets the debugging requirements of complex multi-core SoC, which has a certain practical value.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN47

【参考文献】