应用于移动支付的单线全双工SWP接口电路设计

发布时间：2018-04-22 09:02

本文选题：移动支付 + 高性能　；参考：《华中科技大学》2015年硕士论文

【摘要】：近场支付基于近距离无线通信技术,能够方便的应用于手机、PDA、平板电脑等嵌入式智能设备,在目前国内主流的进场支付方案中,SWP接口就是SIM卡与CLF前端芯片之间的单线全双工通信接口。首先,SWP接口使用单线全双工通信,需要在电路中实现双向信号调制,将收、发信号合成到单线上,达到减少芯片管脚使用的目的,并且电路规模不能太复杂,这样既符合SIM卡的尺寸规范,又实现了NFC功能的扩展。其次,SWP接口需要在短时间内传输大量数据,因此SWP接口的通信性能是本设计中必须重视的一点。在系统设计方面,将SWP接口电路挂载到高吞吐率的AHB总线上,为SWP电路设计了专用的DMA通道。另外,在基带信号处理时,实现了全并行数据收发和通信速率自适应。本设计在后文的FPGA评估中表明,电路面积375SLICE单元,通信速率达到1Mbps,有效数据244.14Kbyte/s,相对于UART串行接口的通信速率19.2Kbps,有效数据2.34Kbyte/s,性能有明显优势。再次,SWP接口应用于移动嵌入式平台,对电路低功耗要求较高。因此设计了低功耗的状态控制器,能够实时的切换电路工作模式。并且在系统设计中加入了时钟管理模块,在电路逻辑综合中加入了自动门控模式,通过这些方法降低了电路功耗。在后文的功耗评估中可知,SWP工作在低功耗模式时的功耗几乎为零,正常工作时在1.2mw左右。国外SWP接口IP价格昂贵,且购买方无自主知识产权。国内部分公司设计的SWP接口电路规模较大,电路结构复杂。本文SWP接口基于SMIC 130nm PFLASH工艺,电路面积为10K个等校门,成功流片后使用MP300测试仪进行测试,测试结果表明本文SWP接口通信速率达到1Mbps,无数据丢包、误码等现象。
[Abstract]:Near field payment is based on close range wireless communication technology. It can be conveniently applied to embedded intelligent devices such as mobile phone, PDA, tablet computer and so on. In the current domestic mainstream payment scheme, the SWP interface is a single line full duplex communication interface between SIM card and CLF front end chip. First, the SWP interface uses single line full duplex communication and needs to be in the circuit In this way, bidirectional signal modulation is realized, the receiving and sending signal is synthesized on the single line to reduce the use of the chip foot, and the circuit size can not be too complex. This not only conforms to the size specification of the SIM card, but also realizes the expansion of the NFC function. Secondly, the SWP interface needs to transmit a large amount of data in a short time, so the communication performance of the SWP interface is this In the design of the system, the SWP interface circuit is mounted on the high throughput AHB bus, and a special DMA channel is designed for the SWP circuit. In addition, the full parallel data transceiver and the communication rate adaptive are realized when the baseband signal is processed. This design shows the circuit area 375SLICE single in the FPGA evaluation of the later text. The communication rate is 1Mbps, the effective data is 244.14Kbyte/s, the communication rate of the UART serial interface is 19.2Kbps, the effective data 2.34Kbyte/s, the performance has the obvious advantage. Again, the SWP interface is applied to the mobile embedded platform, and the low power demand of the circuit is higher. Therefore, the low power state controller is designed, and the real-time switching circuit can be designed. The clock management module is added to the system design, and the automatic gate control mode is added to the logic synthesis of the circuit. The power consumption of the circuit is reduced by these methods. The power consumption of SWP in the low power consumption mode is almost zero at the low power consumption mode, and it is working at about 1.2MW at the normal working time. The foreign SWP interface IP price is high. The SWP interface circuit designed by some domestic companies is large and the circuit structure is complex. The SWP interface is based on the SMIC 130nm PFLASH technology and the circuit area is 10K. After the successful flow sheet, the MP300 tester is used to test it. The test results show that the communication rate of SWP interface reaches 1Mbps, numerous and numerous. According to a packet loss, a bit of error, and so on.

【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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