多核数字信号处理系统中高速缓存配置与布局研究

发布时间：2018-02-02 05:34

本文关键词： 高速缓存高速缓存配置多级高速缓存架构分布式共享高速缓存多核一致性协议数据预取　出处：《南京大学》2017年硕士论文　论文类型：学位论文

【摘要】：处理器与存储器性能之间的剪刀差现象和多核发展的趋势,使存储墙问题越来越严重,高速的存储体系成为高性能计算的保证。多核环境下的片上存储高速缓存对提高存储体系性能至关重要。针对多核数字信号处理系统研究高速缓存架构的优化方法,本文基于CACTI和GEM5仿真平台,采用系统仿真方法,对高速缓存进行了详细探索和研究。本文具体研究了高速缓存内部配置、多级高速缓存组织架构和数据预取技术,提出了高速缓存配置和多级高速缓存组织架构优化的方向。(1)一级高速缓存宜配置为2路组相关,二级高速缓存宜配置为8路组相关,缓存块长度配置为32或64字节为佳。(2)二级高速缓存对一级高速缓存容量比较小情况下,独占型包含关系缓存的性能较好,容量比大于8之后包含性关系对性能影响不再显著。(3)对于需要大量数据共享和交互的应用,具有一定分布性的全局共享二级高速缓存相较于簇内共享二级高速缓存能够提供更好的性能。(4)改进的MOESI 一致性协议相对比MESI 一致性协议对系统性能没有显著的提升,根据简单可靠原则,优先考虑采用MESI 一致性协议。(5)相对跨步预取,硬件预取功能的实现宜采用顺序预取机制。
[Abstract]:The problem of memory wall becomes more and more serious because of the scissors difference between processor and memory performance and the trend of multi-core development. High-speed storage system becomes the guarantee of high performance computing. On-chip storage cache in multi-core environment is very important to improve the performance of storage system. Research on the optimization of cache architecture for multi-core digital signal processing system. Law. Based on the simulation platform of CACTI and GEM5, this paper uses system simulation method to explore and study cache in detail. This paper studies the internal configuration of cache in detail. Multi-level cache organization architecture and data prefetching technology. The direction of cache configuration and multi-level cache organizational architecture optimization is proposed. The secondary cache should be configured as 8-channel group correlation, and the buffer block length should be 32 or 64 bytes. Exclusive inclusion relationship caching has better performance, and the impact of inclusion relationships on performance is no longer significant when the capacity ratio is greater than 8) for applications that require a large amount of data sharing and interaction. Global shared secondary cache with certain distribution can provide better performance than shared two-level cache in cluster. The improved MOESI conformance protocol has no significant improvement on system performance compared with MESI conformance protocol. According to the principle of simple and reliable, MESI Conformance Protocol. 5) relative step prefetching is preferred, and the sequential prefetching mechanism should be used to realize the hardware prefetching function.
【学位授予单位】：南京大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP332

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