高速嵌入式动态随机存储器可编程内建自测试设计及优化

发布时间：2018-02-26 13:43

本文关键词： 嵌入式动态随机存储器增益单元可编程内建自测试内建自优化　出处：《复旦大学》2012年硕士论文　论文类型：学位论文

【摘要】：在现代SoC中,嵌入式存储器已经取代逻辑电路占据了芯片的绝大部分面积。而随着便携式移动电子设备的快速发展,嵌入式存储器的一个分支——嵌入式动态随机存储器又以其高存储密度和低功耗得到了越来越广泛的应用。在这种情况下,整个芯片的良率越来越多地受到其中的存储器模块的影响,对嵌入式存储器的有效测试也因此变得尤为重要。本文介绍了一种高速嵌入式动态随机存储器。该存储器采用新型的2T增益单元结构作为存储单元,具有高存储密度、高访问速度、非破坏性读写、与标准逻辑工艺兼容等优势。该存储器所具有的优势给测试带来了挑战,如何节省测试时间和芯片管脚,在高速测试中保证高故障覆盖率成为重要的问题。针对这一问题,本文提出了一种可编程内建自测试方案。该方案包括了指令集设计和硬件电路的设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令实现多种类型的测试算法,包括March算法、Galpat算法、Hammer test等。该内建自测试模块被集成在了一个存储容量为16KB的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明该内建自测试方案可以在200MHZ的时钟频率下对待测存储器执行全速测试,并实现多种测试算法。针对在上述芯片测试过程中发现的工艺波动导致单元良率降低的问题,本文又介绍了一种能够自动优化存储器性能的可编程内建自测试方案。该方案可以自动优化芯片操作时序,并可以对动态存储单元的数据保持时间进行测试。芯片测试表明,这种改进的可编程内建自测试模块的引入提高了单元良率,并成功测试出了存储器的数据保持时间。本文针对新型的增益单元动态随机存储器提出的可编程内建自测试设计方案及其优化保证了较高的故障覆盖率,提高了测试速度,降低了对自动测试设备的性能要求,降低了芯片管脚消耗,并具有了内建自优化的能力,是对嵌入式存储器测试技术的有益探索与尝试。
[Abstract]:In modern SoC, embedded memory has taken the place of logic circuit to occupy most of the chip area. But with the rapid development of portable mobile electronic devices, Embedded dynamic random access memory, a branch of embedded memory, is more and more widely used for its high storage density and low power consumption. The yield of the whole chip is more and more influenced by the memory module, so it is very important to test the embedded memory effectively. In this paper, a high speed embedded dynamic random access memory (DRAM) is introduced, which uses a new 2T gain cell structure as memory cell. It has high storage density, high access speed, non-destructive reading and writing. Compatible with standard logic process and other advantages. The advantages of the memory have brought challenges to the test. How to save test time and chip pin and ensure high fault coverage in high-speed testing becomes an important problem. This paper presents a programmable built-in self-test scheme, which includes instruction set design and hardware circuit design. The introduction of four-level instruction pipeline makes full speed testing possible. The same test instruction implements many kinds of test algorithms, The built-in self-test module is integrated into an embedded dynamic random access memory chip with a memory capacity of 16KB. The chip test results show that the built-in self-test scheme can perform full-speed test on the test memory at the clock frequency of 200MHZ, and realize various testing algorithms. In view of the problem that the process fluctuation found in the process of testing the chip above leads to the reduction of unit yield, This paper also introduces a programmable built-in self-test scheme which can automatically optimize memory performance. This scheme can automatically optimize the timing of chip operation and test the data retention time of dynamic memory unit. The introduction of the improved programmable build-in self-test module improves the unit yield and successfully tests the data retention time of the memory. In this paper, a programmable built-in self-test design scheme and its optimization for a new type of gain cell dynamic random access memory (DRAM) are proposed to ensure high fault coverage, improve the test speed, and reduce the performance requirements of the automatic test equipment. It reduces the chip pin consumption and has the ability of built-in self-optimization. It is a useful exploration and attempt for embedded memory testing technology.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP333.8

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