基于FPGA的多核处理器系统的研究与设计

发布时间：2018-05-05 18:03

本文选题：FPGA + 多核处理器　；参考：《燕山大学》2013年硕士论文

【摘要】：近年来，测试测量领域中需要进行大数据量处理的情况越来越多，一些复杂测试系统对于数据处理的实时性和准确性要求越来越高。目前多数的处理器，如单片机、数字信号处理器DSP等已无法满足人们的需求。现场可编程门阵列FPGA作为嵌入式SOC设计的载体，具有体积小、功耗低、可靠性好的优点，基于FPGA的多核处理器系统可实现系统的协同工作，可有效解决测试测量领域中多通道数据采集和海量数据并行处理等问题。本文以Xilinx Spartan-3E开发板为设计平台，运用Xilinx ISE软件和EDK套件，实现以32位软核MicroBlaze为处理器模块的片上多核互连的总体设计、硬件设计、核间通信的软件测试以及单核与多核系统性能对比。主要工作如下：设计一种采用FSL总线进行核间通信的单PLB总线方式的多核系统结构来优化资源利用率，提高核间传输速度；利用ISE软件在Spartan-3E开发板上创建自定义FIFO，将自定义FIFO作为核间通信机制，在Xilinx平台工作室XPS中搭建多核系统硬件平台，并完成对硬件的配置。基于搭建的硬件系统平台，借助Xilinx SDK中在线调试工具XMD，通过在多核上添加测试程序实现系统通信结果显示；利用逻辑分析仪Chipscope Pro追踪FPGA内部信号实现片内调试。为实现对单核与多核系统性能的客观评价，从算法执行时间和资源占用率两方面考虑，，分析结果表明多核系统由于采用并行环路体系，并摒弃单核阻塞状态下的等待时间，可以达到处理时间上的优化；而多核系统的资源占用率较单核要高些。
[Abstract]:In recent years, there are more and more cases in the field of testing and measurement that need to be processed with large amount of data. Some complex test systems require more and more real-time and accuracy of data processing. At present, most processors, such as single chip computer, digital signal processor (DSP), can not meet the needs of people. As the carrier of embedded SOC design, field programmable gate array (FPGA) has the advantages of small volume, low power consumption and good reliability. The multi-core processor system based on FPGA can realize the cooperative work of the system. It can effectively solve the problems of multi-channel data acquisition and mass data parallel processing in the field of test and measurement. In this paper, Xilinx Spartan-3E development board is used as design platform, Xilinx ISE software and EDK suite are used to realize the overall design and hardware design of multi-core interconnection on chip with 32-bit soft core MicroBlaze as processor module. Software testing for intercore communication and performance comparison between single core and multi-core systems. The main tasks are as follows: A multi-core system structure based on single PLB bus with FSL bus for inter-core communication is designed to optimize the utilization of resources and improve the transmission speed between cores. The self-defined FIFO is created on the Spartan-3E development board by using ISE software. The self-defined FIFO is used as the communication mechanism between cores. The multi-core system hardware platform is built in the XPS of Xilinx platform studio, and the hardware configuration is completed. Based on the hardware system platform and with the help of the on-line debugging tool XMD in Xilinx SDK, the system communication results are displayed by adding test program to the multi-core, and the on-chip debugging is realized by using the logic analyzer Chipscope Pro to track the internal signal of FPGA. In order to evaluate the performance of single-core system and multi-core system objectively, the algorithm execution time and resource occupancy are considered. The results show that the multi-core system adopts parallel loop system and abandons the waiting time in single-core blocking state. The processing time can be optimized, and the resource occupancy of multi-core system is higher than that of single core system.
【学位授予单位】：燕山大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332

【参考文献】