M5-EDGE分布式取指模型设计
发布时间：2018-08-19 15:18
【摘要】：为解决M5-edge模拟器的理想化集总式取指令结构对基于EDGE体系结构设计空间探索的限制问题,对原模拟器的取指令前段进行分布式设计,包括总体的功能、具体的取指单元及单元间的互连网络设计,并在取指令块头的方式上设计了固定方式和循环方式两种方案.通过对实现后的结构进行在不同分布单元数量条件下的仿真分析,得到从理想集总式取指结构到实际分布式结构的性能下降关系和不同取指令块头方式的优劣.通过进一步分析,得出通信延迟和缓存缺失率对处理器性能的影响.
[Abstract]:In order to solve the problem that the idealized lumped instruction structure of M5-edge simulator limits the exploration of design space based on EDGE architecture, the distributed design of the former simulator is carried out, including the overall function. The design of the interconnect network between the reference unit and the unit, and the design of the fixed mode and the cyclic mode in the way of taking the instruction block are also presented in this paper. Through the simulation and analysis of the realized structure under the condition of different number of distributed units, the relationship between the performance degradation of the ideal lumped reference structure and the actual distributed structure and the advantages and disadvantages of different instruction block methods are obtained. Through further analysis, the effect of communication delay and cache missing rate on processor performance is obtained.
【作者单位】： 哈尔滨工业大学航天学院;
【分类号】：TP332
，
本文编号：2192050
[Abstract]:In order to solve the problem that the idealized lumped instruction structure of M5-edge simulator limits the exploration of design space based on EDGE architecture, the distributed design of the former simulator is carried out, including the overall function. The design of the interconnect network between the reference unit and the unit, and the design of the fixed mode and the cyclic mode in the way of taking the instruction block are also presented in this paper. Through the simulation and analysis of the realized structure under the condition of different number of distributed units, the relationship between the performance degradation of the ideal lumped reference structure and the actual distributed structure and the advantages and disadvantages of different instruction block methods are obtained. Through further analysis, the effect of communication delay and cache missing rate on processor performance is obtained.
【作者单位】： 哈尔滨工业大学航天学院;
【分类号】：TP332
，
本文编号：2192050
本文链接：https://www.wllwen.com/kejilunwen/jisuanjikexuelunwen/2192050.html
