高速数传调制解调器设计与实现

发布时间：2018-01-14 07:12

本文关键词：高速数传调制解调器设计与实现　出处：《南京理工大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着信息通信技术的飞速发展,对通信速率的要求越来越高,如今的通信系统已越来越难以满足不断增长的通信速率需求。在通信系统中,调制解调器的速率往往决定了整个系统的传输速率。因此对高速数传调制解调器的研究已日益成为热点。对于高速数传调制解调器来说,其处理速率主要受限于其所使用芯片的时钟频率。若要突破这一限制,就需要将调制解调器传统的串行结构改为并行结构。本文对此进行了研究,从而给出一套并行的高速数传调制解调器方案。本文首先分析了高速数传调制解调器的各方面细节对其速率和资源的影响,进而确定了调制方式、并行路径数、接收机结构等一系列相关细节,划定了总体的方案框架。然后研究了调制解调器各步骤的理论和常用算法,重点研究了各步骤的并行实现算法,从而给出了各步骤的并行实现方案。其中调制器部分主要有并行的差分编码、并行的时域成形滤波、免混频的正交上变频。解调器部分主要包括频域匹配滤波、频域定时相偏校正、通过增删采样点实现的定时频偏校正、经近似处理优化的并行盲均衡、在极坐标系实现检测和校正的载波同步以及改进的并行差分解码。这些方案都能以较少的资源消耗实现相应功能,它们的Matlab和Modelsim仿真结果也显示了方案的高效性。最后本文在FPGA开发板ML605上对该高速并行调制解调器系统进行了实验测试,测试结果也表明该高速并行调制解调器性能良好。
[Abstract]:With the rapid development of information and communication technology, the communication rate of the increasingly high demand, communication system nowadays has become increasingly difficult to meet the growing demand. The rate of communication in a communication system, modem speed often determines the transmission rate of the whole system. So the research of high speed digital modem has become a hot issue for. High speed digital modem, the processing rate is mainly limited by the use of chip clock frequency. To overcome this limitation, we need the serial structure modem instead of the traditional parallel structure. This paper conducted a study, which gives a parallel high-speed digital modem scheme. This paper analyzes the impact of high speed the number of modems in all aspects of the details of the rate and resources, and to determine the modulation, parallel path number, receiver node Construction of a series of related details, delineation of the overall framework. And then study the various steps of the modem theory and algorithms, focuses on the parallel algorithm of each step, and gives the steps of the parallel program. The main line of the modulator part and the differential encoding, parallel time domain shaping filter orthogonal mixer free frequency. The demodulator includes matched filtering in frequency domain, the frequency domain phase timing offset correction, by adding or deleting the sampling points to achieve timing frequency offset correction, the approximate parallel blind equalization optimization, implementation of parallel finite difference code and carrier detection and correction of the synchronization and improved in the polar coordinate system. These programs are to achieve the corresponding function with less resource consumption, their Matlab and Modelsim simulation results show the efficiency of the scheme. Finally, based on the FPGA development board ML605 of the high speed and The system of the modem is tested, and the results also show that the high speed parallel modem has good performance.

【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN915.05

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