基于SOPC系统的国家商务密码SM4 IP设计与测试

发布时间：2018-01-27 17:02

本文关键词： SM4分组密码算法 SOPC Verilog HDL NiosⅡ 串口　出处：《深圳大学》2016年硕士论文　论文类型：学位论文

【摘要】：在信息社会里,信息资源已经成为国家、企业等团体的重要的战略资源,人们对信息安全越来越重视。国家商务密码管理中心颁布了一系列的密码行业标准,以保护私密的数据信息和在开放链路中通信的数据信息。密码行业标准中包括SM4分组密码算法,SM4算法广泛应用于金融卡、社保卡、无线通信、数据资料等需要对信息进行加密解密处理的领域。本文对SM4分组密码算法进行了分析和研究,编写SM4的C语言代码,并进行软件加密解密测试,以验证分析的正确性。用Verilog HDL语言对SM4分组密码算法进行硬件设计。并对其进行了两种方式的测试。一种方式是在ModelSim软件上进行仿真,编写测试文件,产生激励信号、明文、密钥数据输入到SM4模块进行加密和解密操作,然后读取加密解密的结果以验证其正确性。由于在ModelSim上只能进行功能仿真,无法验证SM4的时序和真实的硬件工作状态,且仿真的速度非常缓慢,进行大数据量的测试耗时非常长。因此另外一种测试方式就是结合PC快速的数据处理能力和FPGA快速硬件生成能力组建测试系统。首先在FPGA芯片上搭建SOPC系统,把SM4封装成IP模块,嵌入到SOPC系统里,然后通过串口和PC相连接,组成测试系统。由PC产生大量的测试数据发送到SOPC系统上,SOPC系统接收到数据以后转给SM4模块,并启动加密解密操作得到加密结果,然后SOPC再把操作结果通过串口发送回PC对结果进行判定结果是否正确。这种测试方法可以验证SM4模块在接近真实硬件工作状态时,对SM4进行大数据量、长时间、高速工作状态时的稳定性、可靠性进行评估。从长时间测试的结果和测试速度来看(相对于ModelSim),SM4硬件模块和搭建的测试系统还是成功的,但本测试系统也有许多不足,因为是针对SM4搭建的测试系统,专用性太强。连接SOPC系统和PC的串口的通信速度最大只能达到115200bit/s,是提高测试速度的瓶颈。
[Abstract]:In the information society, information resources have become an important strategic resource of the country, enterprises and other groups. People pay more and more attention to information security. The National Business password Management Center has issued a series of cryptographic industry standards. The cryptographic industry standard includes SM4 block cipher algorithm (SM4), which is widely used in financial card, social security card and wireless communication. This paper analyzes and studies the SM4 block cipher algorithm, compiles the C language code of SM4, and carries on the software encryption and decryption test. To verify the correctness of the analysis. Use Verilog. HDL language designs the SM4 block cipher algorithm in hardware, and tests it in two ways. One way is to simulate it on ModelSim software. Write test files, generate incentive signals, plaintext, key data input to the SM4 module for encryption and decryption operations. Then read the results of encryption and decryption to verify its correctness. Because of the only functional simulation on ModelSim, it is impossible to verify the timing of SM4 and the real working state of the hardware. And the speed of simulation is very slow. It takes a lot of time to test a large amount of data, so another way of testing is to combine the fast data processing ability of PC and the fast hardware generation ability of FPGA to build a test system. First of all, the test system is built on the FPGA chip. Build SOPC system. The SM4 is encapsulated into IP module, embedded in SOPC system, and then connected with PC through serial port to form a test system. A large number of test data are generated by PC and sent to SOPC system. After receiving the data, the SOPC system transfers the data to the SM4 module and starts the encryption and decryption operation to get the encryption result. Then SOPC sends the operation result back to PC through serial port to determine whether the result is correct. This testing method can verify that the SM4 module is close to the real hardware working state. Evaluate the stability and reliability of SM4 in large amount of data, long time, high speed working condition. From the result of long time test and test speed (relative to Model Sims). SM4 hardware module and built test system is still successful, but this test system also has many shortcomings, because it is the test system built for SM4. The maximum speed of serial port communication between SOPC system and PC is 115200 bit / s, which is the bottleneck to improve the test speed.
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN918.4

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